Mirrored contact CMOS with self-aligned source, drain, and back-gate
A semiconductor device and method of forming a semiconductor device including an inverted field effect transistor having metal filled front-side source and drain that is self-aligned and in direct contact with a metal filled back-side source and drain, wherein the device includes a metal backgate.
1. A semiconductor device comprising:
a silicon-on-insulator layer adhered to a first surface of a buried oxide layer;
at least one gate extending from the silicon-on-insulator layer;
a first dielectric layer deposited over the at least one gate;
a handling wafer adhered to the first dielectric layer;
a front-side source and a front-side drain extending through a portion of the buried oxide layer and silicon-on-insulator layer;
a second dielectric layer deposited on a second surface of the buried oxide layer and a surface of the front-side source and the front-side drain;
a metal back-gate layer applied to the second dielectric layer, wherein the metal back-gate layer is not in contact with the front-side source and the front-side drain;
a third dielectric layer deposited on the metal back-gate layer;
a back-side source and a back-side drain extending through the second dielectric layer, wherein the back-side source is aligned and in contact with the front-side source, wherein the back-side drain is aligned and in contact with the front-side drain; and
a metal back-gate contact extending through the third dielectric layer to a portion of the metal back-gate layer.
2. The semiconductor device of claim 1 wherein the front-side source and the front-side drain are independently filled with a metal selected from tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
3. The semiconductor device of claim 1 wherein the back-side source and the back-side drain are independently filled with a metal selected from copper, tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
4. The semiconductor device of claim 1 wherein the metal back-gate layer includes titanium nitride.
5. The semiconductor device of claim 1 further comprising a bonding layer between the first dielectric layer and the handling wafer.
6. The semiconductor device of claim 1 wherein the device includes gate spacers adjacent to the gate adjoining a gate conductor line.
7. A method of fabricating an upside-down field effect transistor, the method comprising:
providing a donor substrate including a silicon substrate, a buried oxide, and a single-crystal silicon-on-insulator layer;
forming a gate extending from the silicon-on-insulator layer;
forming a front-side source and a front-side drain in the donor substrate by etching a portion of the donor substrate and filling the etched regions with a first metal;
depositing and planarizing a first dielectric layer over the gate, the front-side source, and the front-side drain;
adhering the dielectric layer to a handling wafer;
selectively removing the donor substrate to expose the buried oxide layer, a portion of the front-side source, and a portion of the front-side drain;
depositing a second dielectric layer over the exposed buried oxide layer, the exposed portion of the front-side source, and the exposed portion of the front-side drain;
depositing a metal back-gate layer over the second dielectric layer;
depositing a third dielectric layer over the metal back-gate layer, the exposed portion of the front-side source, and the exposed portion of the front-side drain;
forming a back-side source and a back-side drain in the third dielectric layer, wherein the back-side source is aligned and in contact with the front-side source, wherein the back-side drain is aligned and in contact with the front-side drain; and
forming a back-gate metal contact in the third dielectric layer, wherein the back-gate metal contact is in contact with a portion of the back-gate metal layer.
8. The method of claim 7 wherein the device includes gate spacers adjacent to the gate adjoining a gate conductor line.
9. The method of claim 7 wherein adhering the first dielectric layer to a handling wafer includes depositing a bonding film between the handling wafer and the first dielectric layer.
10. The method of claim 7 wherein the front-side source and the front-side drain are independently filled with a metal selected from tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
11. The method of claim 7 wherein the back-side source and the back-side drain are independently filled with a metal selected from copper, tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
12. The method of claim 7 wherein the metal back-gate layer includes titanium nitride.
13. The method of claim 7 further comprising a bonding layer between the first dielectric layer and the handling wafer.
14. A method of fabricating an upside-down field effect transistor, the method comprising:
providing a donor substrate including a silicon substrate, a buried oxide, and a single-crystal silicon-on-insulator layer;
forming a gate extending from the silicon-on-insulator layer;
forming a front-side source and a front-side drain in the donor substrate by etching a portion of the donor substrate and filling the etched regions with a first metal;
depositing and planarizing a first dielectric layer over the gate, the front-side source, and the front-side drain;
adhering the first dielectric layer to a handling wafer;
selectively removing the donor substrate to expose the buried oxide layer, a portion of the front-side source, and a portion of the front-side drain;
depositing a second dielectric layer over the exposed buried oxide layer, the exposed portion of the front-side source, and the exposed portion of the front-side drain;
selectively removing portions of the second dielectric layer to expose a surface of the buried oxide layer, a top surface of the front-side source, and a top surface of the front-side drain, wherein the second dielectric layer remains in contact with a sidewall of the front-side source and a sidewall of the front-side drain;
depositing a metal back-gate layer over the second dielectric layer;
depositing a third dielectric layer over the metal back-gate layer, the exposed portion of the front-side source, and the exposed portion of the front-side drain;
forming a back-side source and a back-side drain in the third dielectric layer, wherein the back-side source is aligned and in contact with the front-side source, wherein the back-side drain is aligned and in contact with the front-side drain; and
forming a back-gate metal contact in the third dielectric layer, wherein the back-gate metal contact is in contact with a portion of the back-gate metal layer.
15. The method of claim 14 wherein adhering the first dielectric layer to a handling wafer includes depositing a bonding film between the handling wafer and the first dielectric layer.
16. The method of claim 14 wherein adhering the first dielectric layer to a handling wafer includes depositing a bonding film between the handling wafer and the first dielectric layer.
17. The method of claim 14 wherein the front-side source and the front-side drain are independently filled with a metal selected from tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
18. The method of claim 14 wherein the back-side source and the back-side drain are independently filled with a metal selected from copper, tungsten, cobalt ruthenium, nickel, titanium, silicide, or combinations thereof.
19. The method of claim 14 wherein the metal back-gate layer includes titanium nitride.
20. The method of claim 14 further comprising a bonding layer between the first dielectric layer and the handling wafer.