Adjusting latency in a scan cell

Inventors: Steven M. Douskey (Rochester, MN); Raghu G. Gopalakrishnasetty (Bangalore, IN); Mary P. Kusko (Hopewell Junction, NY)

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

G01R31/2882 G01R31/3177 G01R31/31701

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Quick Facts

Patent No.: US 10,001,523
App. No.: 15/238,477
Granted: Jun 19, 2018
Kind: B2

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Abstract

Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.

Claims (30)

1. An integrated circuit, comprising:

a plurality of serially connected scan cells for testing the integrated circuit, wherein each of the scan cells comprises a multiplexer, and wherein the multiplexer comprises:

a first input stage configured to receive scan input data, wherein the first input stage is coupled to first selection logic;

a second input stage configured to receive functional input data, wherein the second input stage is coupled to second selection logic, and wherein the first and second selection logic are configured to select between the first and second input stages according to a scan enable signal, wherein the scan enable signal changes the scan cell between a test mode and a normal functioning mode; and

delay logic coupled to the first selection logic, wherein the delay logic comprises a plurality of delay elements, and wherein the delay logic is configured to activate the plurality of delay elements based on whether the first selection logic selects the first input stage according to the scan enable signal and wherein a first subset of the plurality of delay elements is activated when a clock signal is low and a second subset of the plurality of delay elements is activated when the clock signal is high, thereby increasing a scan latency of the scan cell relative to when the second selection logic selects the second input stage.

2. The integrated circuit of claim 1 , wherein the delay logic is coupled to the first input stage.

3. The integrated circuit of claim 2 , wherein the delay logic is coupled to the first input stage through a plurality of internal nodes connected to the first input stage.

4. The integrated circuit of claim 1 , wherein the delay logic is configured to activate the plurality of delay elements to change a potential of a plurality of internal nodes connected to the first selection logic, thereby changing the scan latency of the scan cell.

5. The multiplexer of claim 1 , wherein the clock signal is applied via an inverter to a gate of a transistor of the second subset of the plurality of delay elements as a not clock signal.

6. The integrated circuit of claim 1 , wherein the delay logic is configured to activate the plurality of delay elements to delay a rise and fall transition time on an output path of the first input stage, thereby increasing the scan latency of the scan cell.

7. The integrated circuit of claim 1 wherein the clock signal is applied to a gate of a transistor of the second subset of the plurality of delay elements as a low clock signal.

8. A multiplexer within a scan cell for testing an integrated circuit, comprising:

a first input stage configured to receive scan input data, wherein the first input stage is coupled to first selection logic;

delay logic coupled to the first selection logic, wherein the delay logic comprises a plurality of delay elements, and wherein the delay logic is configured to activate the delay elements based on whether the first selection logic selects the first input stage according to the scan enable signal and wherein a first subset of the plurality of delay element is activated when a clock signal is low and a second subset of the plurality of delay elements is activated when the clock signal is high, thereby increasing a scan latency of the scan cell relative to when the second selection logic selects the second input stage.

9. The multiplexer of claim 8 , wherein the delay logic is coupled to the first input stage.

10. The multiplexer of claim 9 , wherein the delay logic is coupled to the first input stage through a plurality of internal nodes connected to the first input stage.

11. The multiplexer of claim 8 , wherein the delay logic is configured to activate the plurality of delay elements to change a potential of a plurality of internal nodes connected to the first selection logic, thereby changing the scan latency of the scan cell.

12. The multiplexer of claim 8 , wherein the clock signal is applied via an inverter to a gate of a transistor of the second subset of the plurality of delay elements.

13. The multiplexer of claim 8 , wherein the delay logic is configured to activate the plurality of delay elements to delay a rise and fall transition time on an output path of the first input stage, thereby increasing the scan latency of the scan cell.

14. The multiplexer of claim 8 , wherein the clock signal is applied to a gate of a transistor of the second subset of the plurality of delay elements as a low clock signal.

15. A method, comprising:

receiving a scan enable signal at a scan cell, wherein the scan enable signal changes the scan cell between a test mode and a normal functioning mode;

selecting between first and second input stages within the scan cell according to the scan enable signal, wherein the first input stage is configured to receive scan input data and the second input stage is configured to receive functional input data; and

activating a plurality of delay elements of a delay logic coupled to the first input stage based on whether the first input stage is selected according to the scan enable signal and wherein a first subset of the plurality of delay elements is activated when a clock signal is low and a second subset of the plurality of delay elements is activated when the clock signal is high, thereby increasing a scan latency of the scan cell relative to when the second selection logic selects the second input stage.

16. The method of claim 15 , wherein the delay logic is coupled to the first input stage.

17. The method of claim 16 , wherein the delay logic is coupled to the first input stage through a plurality of internal nodes connected to the first input stage.

18. The method of claim 15 , wherein the delay logic is configured to activate the plurality of delay elements to change a potential of a plurality of internal nodes connected to the first input stage, thereby changing the scan latency of the scan cell.

19. The method of claim 15 , wherein the delay logic is configured to activate the plurality of delay elements according to a clock signal, wherein the clock signal is applied to a gate of a transistor of the delay elements.

20. The method of claim 15 , wherein the delay logic is configured to activate the plurality of delay elements to delay a rise and fall transition time on an output path of the first input stage, thereby increasing the scan latency of the scan cell.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2016

From: DOUSKEY, STEVEN M.; GOPALAKRISHNASETTY, RAGHU G.; KUSKO, MARY P.

To: INTERNATIONAL BUSINESS MACHINES CORPORATION

Reel/Frame 039458/0818 →

Continuity (1)

Related Publication 20180052198A1 · Feb 22, 2018