Variable-length instruction buffer management
A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
1. A computer-implemented method for managing a variable-length instruction buffer, comprising:
caching variable-length instruction data from a first reference location;
comparing a first level of unprocessed data available in an instruction buffer at a first time to a default threshold;
loading a fixed width of data from the cached instruction data into the instruction buffer based on the first level of unprocessed data not satisfying the default threshold;
processing a branching instruction referencing a second reference location different from the first reference location, the branching instruction including a header indicating a branch delay size;
comparing a second level of unprocessed data available in the instruction buffer at a second time after the branching instruction is processed to the branch delay size; and
loading a fixed width of data from the cached instruction data into the buffer based on the second level of unprocessed data not satisfying the branch delay size.
2. The method of claim 1 , further comprising:
decoupling a variable-length instruction from the unprocessed data in the buffer and outputting the decoupled instruction, reducing the level of unprocessed data in the buffer.
3. The method of claim 2 , wherein the decoupled instruction is output to a vector processor.
4. A system for managing variable-length instructions, comprising:
a cache for storing variable-length instructions from memory, the cache configured to load instructions from a particular memory location;
a buffer for decoupling data loaded from the cache into instructions, the buffer configured to receive fixed-width data lines from the cache and output variable-length instructions; and
a fetch unit configured to determine a level of unprocessed data in the buffer and instruct the cache to load additional data into the buffer;
wherein the fetch unit is further configured to:
compare a first level of unprocessed data available in the buffer at a first time to a default threshold to determine when to instruct the cache to load additional data into the buffer;
after the system identifies a branching instruction, determine a branch delay size from the branching instruction header; and
compare a second level of unprocessed data available in the buffer at a second time after the system identifies the branching instruction to the branch delay size instead of the default threshold to determine when to instruct the cache to load additional data into the buffer.