IP Library › Granted Patent US 10,014,879
Granted Patent B1
US 10,014,879 · App. 15/827,530 · Granted Jul 3, 2018

Capacitance-to-digital converter

Inventors: Ramin Zanbaghi (Austin, TX); John L. Melanson (Austin, TX)
Assignee: Cirrus Logic, Inc.
H03M3/458G01R19/25G01R27/2605H03M1/12H03M3/362H03M3/384H03M3/43H03M3/438
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Quick Facts
Patent No.
US 10,014,879
App. No.
15/827,530
Filed
Nov 30, 2017
Granted
Jul 3, 2018
Kind
B1
Art Unit
2845
USPC
341/121
Abstract

A method for measuring capacitance may include integrating charge with a charge integrator having a charge integrator input and output, filtering, with a loop filter having a loop filter input coupled to the charge integrator output and having a loop filter output, a first signal generated at the charge integrator output, quantizing, with quantizer having a quantizer input coupled to the loop filter output and a having quantizer output, a second signal generated at the loop filter output, processing, with a first feedback path having a first feedback path input coupled to the quantizer output and a first feedback path output coupled to the charge integrator input, a low-frequency spectrum of a quantizer output signal, and processing, with a second feedback path having a second feedback path input coupled to the quantizer output and a second feedback path output coupled downstream in a signal path of the apparatus relative to the charge integrator, a high-frequency spectrum of the quantizer output signal.

Claims (27)

1. An apparatus for measuring capacitance, comprising:

a charge integrator having a charge integrator input and a charge integrator output;

a first feedback path having a first feedback path input and a first feedback path output, wherein the first feedback path output is coupled to an input of the charge integrator;

a second feedback path having a second feedback path input and a second feedback path output, wherein the second feedback path output is coupled downstream in a signal path of the apparatus relative to the charge integrator;

a loop filter having a loop filter input and a loop filter output, wherein the loop filter input is coupled to the output of the charge integrator and second feedback path output; and

a quantizer having a quantizer input and a quantizer output, wherein the quantizer input is coupled to the loop filter output, the quantizer output is coupled to the first feedback path and the quantizer is configured to quantize a signal generated at the loop filter output;

wherein:

the first feedback path processes a low-frequency spectrum of a quantizer output signal at the quantizer output so that high-frequency quantization noise is filtered from passing through the charge integrator; and

the second feedback path processes a high-frequency spectrum of the quantizer output signal.

2. The apparatus of claim 1 , wherein the first feedback path comprises a digital-to-analog converter.

3. The apparatus of claim 2 , wherein the digital-to-analog converter comprises a switched capacitor digital-to-analog converter.

4. The apparatus of claim 1 , wherein the second feedback path comprises a digital-to-analog converter.

5. The apparatus of claim 4 , wherein the digital-to-analog converter comprises a switched resistor digital-to-analog converter.

6. The apparatus of claim 1 , wherein the loop filter comprises a discrete-time loop filter.

7. The apparatus of claim 1 , wherein the loop filter comprises a delta-sigma modulator.

8. A method for measuring capacitance, comprising:

integrating charge with a charge integrator having a charge integrator input and a charge integrator output;

filtering, with a loop filter having a loop filter input coupled to the charge integrator output and having a loop filter output, a first signal generated at the charge integrator output;

quantizing, with a quantizer having a quantizer input coupled to the loop filter output and a having quantizer output, a second signal generated at the loop filter output;

processing, with a first feedback path having a first feedback path input coupled to the quantizer output and a first feedback path output coupled to the charge integrator input, a low-frequency spectrum of a quantizer output signal at the quantizer output so that high-frequency quantization noise is filtered from passing through the charge integrator; and

processing, with a second feedback path having a second feedback path input coupled to the quantizer output and a second feedback path output coupled downstream in a signal path of the apparatus relative to the charge integrator, a high-frequency spectrum of the quantizer output signal.

9. The method of claim 8 , wherein the first feedback path comprises a digital-to-analog converter.

10. The method of claim 9 , wherein the digital-to-analog converter comprises a switched capacitor digital-to-analog converter.

11. The method of claim 8 , wherein the second feedback path comprises a digital-to-analog converter.

12. The method of claim 11 , wherein the digital-to-analog converter comprises a switched resistor digital-to-analog converter.

13. The method of claim 8 , wherein the loop filter comprises a discrete-time loop filter.

14. The method of claim 8 , wherein the loop filter comprises a delta-sigma modulator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2018
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 045451/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2018
From: ZANBAGHI, RAMIN; MELANSON, JOHN L.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 045427/0982 →
Cited By (1)
US 12,683,627