Image sensor and electronic apparatus including multiple substrates
The present technology relates to an image sensor and an electronic apparatus which can make the image sensor a smaller without degrading performance of the image sensor. The image sensor includes a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, a row circuit configured to control row scanning of the pixel array unit, and a column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is disposed on a first-layer substrate, and the row circuit and the column processing unit are disposed on different substrates which are underlying layers of the first-layer substrate and which are laminated on the first-layer substrate. The present technology is applicable to the image sensor.
1. An image sensor comprising:
a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner;
a row circuit configured to control row scanning of the pixel array unit; and
a column processing unit including a comparator and a counter, the column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal,
wherein the pixel array unit is disposed on a first substrate,
wherein the row circuit is disposed on a second substrate,
wherein the column processing unit is disposed on a third substrate,
wherein the first substrate, the second substrate, and the third substrate are laminated,
wherein the comparator includes a first portion and a second portion,
wherein the counter includes a first portion and a second portion,
wherein the first portions of the comparator and the counter are disposed adjacent to one another on a first region of the third substrate,
wherein the second portions of the comparator and the counter are disposed adjacent to one another on a second region of the third substrate,
wherein, in a plan view, the first portions and the second portions are separated from each other in a vertical direction, and
wherein the first portions and the second portions have equal lengths in a horizontal direction and are aligned with one another in the vertical direction.
2. The image sensor according to claim 1 , wherein a length of the row circuit in the vertical direction is equal to or longer than a length of the pixel array unit in the vertical direction.
3. The image sensor according to claim 1 , wherein a length of the column processing unit in the horizontal direction is equal to or longer than a length of the pixel array unit in the horizontal direction.
4. The image sensor according to claim 1 , wherein the row circuit is disposed on the second substrate such that a central axis of the pixel array unit in the horizontal direction is displaced from a central axis of the row circuit in the horizontal direction.
5. The image sensor according to claim 1 , wherein the column processing unit is disposed on the third substrate such that a central axis of the pixel array unit in the vertical direction is displaced from a central axis of the column processing unit in the vertical direction.
6. The image sensor according to claim 1 , wherein a memory is disposed on the second substrate or the third substrate.
7. The image sensor according to claim 1 ,
wherein the second substrate is disposed between the first substrate and the third substrate.
8. The image sensor according to claim 1 ,
wherein the third substrate is disposed between the first substrate and the second substrate.
9. The image sensor according to claim 1 , further comprising:
a memory disposed adjacent to the row circuit on the second substrate in the plan view, wherein the memory includes memory cells separate from shift registers of the row circuit.
10. The image sensor according to claim 1 ,
wherein an image signal processing circuit is disposed between the first region and the second region of the third substrate in the plan view,
wherein lengths of the first portions and the second portions in the horizontal direction are equal to a length of the pixel array unit in the horizontal direction.
11. The image sensor according to claim 1 ,
wherein an image signal processing circuit is disposed between the first region and the second region of the third substrate in the plan view, and
wherein a memory is disposed adjacent to the row circuit on the second substrate in the plan view.
12. The image sensor according to claim 11 ,
wherein a length of the memory in the vertical direction is equal to a length of the row circuit in the vertical direction in the plan view.
13. The image sensor according to claim 11 ,
wherein the memory on the second substrate overlaps the column processing unit on the third substrate in the plan view, and
wherein the memory on the second substrate overlaps the image signal processing circuit on the third substrate in the plan view.
14. The image sensor according to claim 11 , wherein a length of the pixel array unit in the vertical direction is equal to a length of the memory in the vertical direction in the plan view, and wherein the pixel array unit overlaps the memory on the second substrate in the plan view.
15. The image sensor according to claim 1 ,
wherein the comparator is coupled to a vertical signal line and to a digital-to-analog converter.
16. An electronic apparatus comprising:
an image sensor including
a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner,
a row circuit configured to control row scanning of the pixel array unit, and
a column processing unit including a comparator and a counter, the column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal,
wherein the pixel array unit is disposed on a first substrate,
wherein the row circuit is disposed on a second substrate,
wherein the column processing unit is disposed on a third substrate,
wherein the first substrate, the second substrate, and the third substrate are laminated,
wherein the comparator includes a first portion and a second portion,
wherein the counter includes a first portion and a second portion,
wherein the first portions of the comparator and the counter are disposed adjacent to one another on a first region of the third substrate,
wherein the second portions of the comparator and the counter are disposed adjacent to one another on a second region of the third substrate,
wherein, in a plan view, the first portions and the second portions are separated from each other in a vertical direction, and
wherein the first portions and the second portions have equal lengths in a horizontal direction and are aligned with one another in the vertical direction; and
an image signal processing circuit configured to perform signal processing on a signal output from the image sensor.