Iterative N-detect based logic diagnostic technique

1. A method for an interactive logic diagnostic process for a circuit of a device under test, the method comprising:

applying test patterns to the circuit of the device under test in order to generate results;

determining that a critical failure has occurred in the device from the results; and

performing a diagnostic iteration loop, comprising:

checking whether the critical failure has a diagnostic resolution that meets a predefined diagnostic resolution for physical failure analysis;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, isolating potential faults related to the critical failure;

in response to the critical failure having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, ending the diagnostic iteration loop;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, applying path focused fault test patterns to the device in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because of at least one of:

a number of the potential faults related to the critical failure has decreased, and

a size of a physical area of the potential faults related to the critical failure has decreased; and

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, returning to performing the diagnostic iteration loop;

wherein the diagnostic resolution of the critical failure in the circuit of the device has been increased to provide a physical location in the circuit of the device that identifies the critical failure for physical failure analysis.

2. The method of claim 1 , wherein performing the diagnostic iteration loop is repeated until the critical failure has the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis.

3. The method of claim 1 , wherein generating the path focused fault test patterns comprises identifying fault detection paths for testing the potential faults.

4. The method of claim 3 , wherein generating the path focused fault test patterns comprises selecting a subset of the fault detection paths to the potential faults.

5. The method of claim 4 , wherein applying the path focused fault test patterns to the device comprises using the subset of the fault detection paths.

6. The method of claim 5 , wherein using the subset of the fault detection paths when performing each iteration of the diagnostic iteration loop causes the at least one of:

the number of the potential faults related to the critical failure to decrease, and

the size of the physical area of the potential faults related to the critical failure to decrease.

7. The method of claim 6 , wherein for each iteration of performing the diagnostic iteration loop the subset of the fault detection paths is selected for the at least one of the number of the potential faults that has decreased and the size of the physical area of the potential faults that has decreased.

8. The method of claim 1 , wherein the path focused test patterns are generated from one or more fault models.

9. A computer program product for implementing an interactive logic diagnostic process for a circuit of a device under test, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:

applying test patterns to the circuit of the device under test in order to generate results;

determining that a critical failure has occurred in the device from the results; and

performing a diagnostic iteration loop, comprising:

checking whether the critical failure has a diagnostic resolution that meets a predefined diagnostic resolution for physical failure analysis;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, isolating potential faults related to the critical failure;

in response to the critical failure having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, ending the diagnostic iteration loop;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, applying path focused fault test patterns to the device in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because of at least one of:

a number of the potential faults related to the critical failure has decreased, and

a size of a physical area of the potential faults related to the critical failure has decreased; and

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, returning to performing the diagnostic iteration loop;

wherein the diagnostic resolution of the critical failure in the circuit of the device has been increased to provide a physical location in the circuit of the device that identifies the critical failure for physical failure analysis.

10. The computer program product of claim 9 , wherein performing the diagnostic iteration loop is repeated until the critical failure has the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis.

11. The computer program product of claim 9 , wherein generating the path focused fault test patterns comprises identifying activation paths to the potential faults.

12. The computer program product of claim 11 , wherein generating the path focused fault test patterns comprises selecting a subset of the fault detection paths to the potential faults.

13. The computer program product of claim 12 , wherein applying the path focused fault test patterns to the device under test comprises using the subset of the fault detection paths.

14. The computer program product of claim 13 , wherein using the subset of the fault detection paths when performing each iteration of the diagnostic iteration loop causes the at least one of:

the number of the potential faults related to the critical failure to decrease, and

the size of the physical area of the potential faults related to the critical failure to decrease.

15. The computer program product of claim 13 , wherein for each iteration of performing the diagnostic iteration loop the subset of the fault detection paths is selected for the at least one of the number of the potential faults that has decreased and the size of the physical area of the potential faults that has decreased.

16. The computer program product of claim 11 , wherein the path focused test patterns are generated from one or more fault models.

17. A computer system for an interactive logic diagnostic process for a circuit of a device under test, the system comprising:

a memory; and

a processor, communicatively coupled to the memory, the computer system configured to perform a method comprising:

applying test patterns to the circuit of the device under test in order to generate results;

determining that a critical failure has occurred in the device from the results; and

performing a diagnostic iteration loop, comprising:

checking whether the critical failure has a diagnostic resolution that meets a predefined diagnostic resolution for physical failure analysis;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, isolating potential faults related to the critical failure;

in response to the critical failure having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, ending the diagnostic iteration loop;

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, applying path focused fault test patterns to the device in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because of at least one of:

a number of the potential faults related to the critical failure has decreased, and

a size of a physical area of the potential faults related to the critical failure has decreased; and

in response to the critical failure not having the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis, returning to performing the diagnostic iteration loop;

wherein the diagnostic resolution of the critical failure in the circuit of the device has been increased to provide a physical location in the circuit of the device that identifies the critical failure for physical failure analysis.

18. The computer system of claim 17 , wherein performing the diagnostic iteration loop is repeated until the critical failure has the diagnostic resolution that meets the predefined diagnostic resolution for physical failure analysis.

19. The computer system of claim 17 , wherein generating the path focused fault test patterns comprises identifying fault detection paths to the potential faults.

20. The computer system of claim 19 , wherein generating the path focused fault test patterns comprises selecting a subset of the fault detection paths to the potential faults.