Interconnection structure with confinement layer
An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
1. A method for manufacturing a semiconductor device, comprising:
forming a passivation layer over a top surface of an integrated circuit device;
forming a patterned sacrificial layer over the passivation layer, the patterned sacrificial layer having an opening therein;
forming a conductive line over the integrated circuit device by:
depositing at a first plating rate a first layer of conductive material in the opening; and
depositing at a second plating rate a second layer of the conductive material in the opening on the first layer of conductive material; and
forming a passivation layer over the conductive line.
2. The method of claim 1 , wherein an average grain size of the first layer of conductive material is about 3 times to about 5 times as large as an average grain size of the second layer of the conductive material.
3. The method of claim 1 , wherein an average grain size of the second layer of the conductive material is in a range from about 0.1 microns to about 0.5 microns.
4. The method of claim 1 , wherein the conductive line comprises a contact pad.
5. The method of claim 1 , wherein the second layer of the conductive material has an impurity concentration higher than that of the first layer of conductive material.
6. The method of claim 1 , wherein the first plating rate is about 2 times to about 10 times as fast as the second plating rate.
7. The method of claim 1 , further comprising forming a third layer of the conductive material over the second layer of the conductive material using a multi-step electroplating operation, wherein the multi-step electroplating operation further comprises depositing the third layer of the conductive material at a third plating rate that is faster than the second plating rate.
8. The method of claim 1 , further comprising forming a through substrate via (TSV) electrically and physically connected to the conductive line.
9. A semiconductor device comprising:
a substrate including an electrical component;
a patterned passivation overlying the substrate and the electrical component;
a conductor element electrically connected to the electrical component, the conductor element including:
a first layer of a first metal having a first thickness and a first average grain size, and
a second layer of the first metal, the second layer having a second thickness less than the first thickness and a second average grain size, less than the first average grain size, wherein the second layer inhibits growth of grain boundaries in the first layer; and
a passivation contacting sidewalls of the first layer and the second layer and contacting and partially covering a topmost surface of the second layer.
10. The semiconductor device of claim 9 , further comprising:
a third layer of the first metal over the second layer of the first metal, the third layer of the first metal having a third average grain size greater than the second average grain size.
11. The semiconductor device of claim 9 , wherein the second layer has a thickness ranging from about 0.1 microns to about 0.5 microns.
12. The semiconductor device of claim 9 , further comprising a through via substrate (TSV) electrically connected to the conductor element.
13. The semiconductor device of claim 9 , wherein the second layer has an impurity concentration higher than that of the first layer.
14. The semiconductor device of claim 13 , wherein the impurity comprises nitrogen, sulfur, carbon, oxygen or a combination thereof.
15. The semiconductor device of claim 13 , wherein the impurity concentration of the second layer is 2 times to about 10 times as high as that of the first layer.
16. A semiconductor device comprising:
an integrated circuit; and
a contact pad electrically connected to the integrated circuit, the contact pad including
a bottom pad;
a barrier pad disposed on a top surface of the bottom pad; and
a top pad disposed on the top surface of the barrier pad;
wherein the top pad has a thickness less than a maximum thickness resulting in a crystal structure with a topography at the top pad topmost surface having predetermined maximum variation; and
wherein the barrier pad has a thickness sufficient to prevent the bottom pad from affecting crystal growth of the top pad, and having sufficient thinness to prevent barrier pad surface topography variations greater than a predetermined size.
17. The semiconductor device of claim 16 , wherein the barrier pad has a thickness ranging from about 0.1 microns to about 0.5 microns.
18. The semiconductor device of claim 16 , wherein the top pad has a thickness ranging from about 1 to about 4 microns.
19. The semiconductor device of claim 16 , wherein a thickness of the contact pad is about 1 to about 10 microns.
20. The semiconductor device of claim 16 , further comprising a through substrate via (TSV) electrically and physically connected to the contact pad.