Systems and methods for analog to digital conversion

1. An analog to digital converter (ADC) circuit, comprising:

a first stage configured to:

receive a first analog voltage signal;

convert the first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal; and

generate a first residue voltage signal based on the first analog voltage signal and the first digital signal;

a first amplifier control unit configured to generate a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal;

a first amplifier configured to generate the second analog voltage signal based on the first residue voltage signal in response to the first amplifier start signal;

the second stage configured to:

generate the second stage ready signal;

receive, from the first amplifier, the second analog voltage signal; and

convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal.

2. The ADC circuit of claim 1 , wherein the first stage includes:

a first ADC element configured to convert the first analog voltage signal to the first digital signal;

a first digital-to-analog converter (DAC) configured to convert the first digital signal to a reconverted analog voltage signal; and

a residue voltage generator configured to generate the first residue voltage signal corresponding to a difference between the first analog voltage signal and the reconverted analog voltage signal; and

wherein the first amplifier control unit is configured to generate the first amplifier start signal based on a first stage end signal indicating that the first stage completes processing the first analog voltage signal.

3. The ADC circuit of claim 1 , further comprising:

a timing controller configured to:

receive a reference clock signal;

receive, from the first stage, a first stage ready signal indicating that the first stage is ready to process the first analog voltage signal; and

generate a sampling clock signal based on the first stage ready signal and the reference clock signal; and

a sampling circuit configured to:

generate the first analog voltage signal by sampling an analog input signal based on the sampling clock signal.

4. The ADC circuit of claim 3 , wherein the timing controller is configured to generate a first stage start signal based on the sampling clock signal; and

wherein the first stage is configured to:

receive the first stage start signal; and

in response to the first stage start signal, start to convert the first analog voltage signal to the first digital signal.

5. The ADC circuit of claim 3 , wherein the timing controller is configured to:

generate the sampling clock signal based on a first sampling frequency; and

generate a sampling frequency status flag indicating the first sampling frequency exceeds a maximum sampling frequency of the ADC circuit.

6. The ADC circuit of claim 3 , wherein the timing controller is configured to:

generate a missed sample flag indicating that the ADC circuit misses a first sample of the analog input signal based on the sampling clock signal and the first stage ready signal.

7. The ADC circuit of claim 1 , wherein the first amplifier is configured to:

provide a first amplifier end signal indicating that the first amplifier completes generating the second analog voltage signal;

wherein the first stage is configured to reset a plurality of components of the first stage in response to the first amplifier end signal; and

wherein the second stage is configured to start to convert the second analog voltage signal to the second digital signal in response to the first amplifier end signal.

8. The ADC circuit of claim 1 , wherein the second stage is configured to:

generate a second stage end signal indicating that the second stage completes processing the second analog voltage signal; and

in response to the second stage end signal, reset a plurality of components of the second stage.

9. The ADC circuit of claim 1 , further comprising:

a second amplifier configured to:

receive, from the second stage, a second residue voltage signal based on the second analog voltage signal and the second digital signal;

receive, from a third stage, a third stage ready signal indicating that the second stage is ready to process a third analog voltage signal; and

in response to the third stage ready signal, generate the third analog voltage signal based on the second residue voltage signal; and

the third stage configured to:

generate the third stage ready signal;

receive, from the second amplifier, the third analog voltage signal; and

convert the third analog voltage signal to a third digital signal including a third portion of the digital output signal.

10. The ADC circuit of claim 1 , wherein the first amplifier is an open loop integrating amplifier.

11. A method, including:

receiving, by a first stage, a first analog voltage signal;

converting, by the first stage, the first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal;

generating, by the first stage, a first residue voltage signal based on the first analog voltage signal and the first digital signal;

generating, by a second stage, a second stage ready signal indicating that the second stage is ready to process a second analog voltage signal;

generating, by a first amplifier control unit, a first amplifier start signal based on the second stage ready signal;

generating, by a first amplifier, the second analog voltage signal based on the first residue voltage signal in response to the first amplifier start signal; and

converting, by the second stage, the second analog voltage signal to a second digital signal including a second portion of the digital output signal.

12. The method of claim 11 , wherein the generating the first residue voltage signal includes:

converting the first digital signal to a reconverted analog voltage signal; and

generating the first residue voltage signal corresponding to a difference between the first analog voltage signal and the reconverted analog voltage signal; and

wherein the generating the first amplifier start signal includes:

generating, by the first amplifier control unit, the first amplifier start signal based on a first stage end signal indicating that the first stage completes processing the first analog voltage signal.

13. The method of claim 11 , further comprising:

receiving a reference clock signal;

receiving, from the first stage, a first stage ready signal indicating that the first stage is ready to process the first analog voltage signal;

generating a sampling clock signal based on the first stage ready signal and the reference clock signal; and

generating the first analog voltage signal by sampling an analog input signal based on the sampling clock signal.

14. The method of claim 13 , further comprising:

generating a first stage start signal based on the sampling clock signal;

receiving, by the first stage, the first stage start signal; and

in response to the first stage start signal, starting, by the first stage, to convert the first analog voltage signal to the first digital signal.

15. The method of claim 13 , further comprising:

generating the sampling clock signal based on a first sampling frequency; and

generating a sampling frequency status flag indicating that the first sampling frequency exceeds a predefined maximum sampling frequency.

16. The method of claim 13 , further comprising:

generating a missed sample flag indicating that the first analog voltage signal misses a first sample associated with the analog input signal based on the sampling clock signal and the first stage ready signal.

17. The method of claim 11 , further comprising:

providing, by the first amplifier, a first amplifier end signal indicating that the first amplifier completes generating the second analog voltage signal;

in response to the first amplifier end signal, resetting, by the first stage, a plurality of components of the first stage; and

in response to the first amplifier end signal, starting, by the second stage to convert the second analog voltage signal to the second digital signal.

18. The method of claim 11 , further comprising:

generating, by the second stage, a second stage end signal indicating that the second stage completes processing the second analog voltage signal; and

in response to the second stage end signal, reset, by the second stage, a plurality of components of the second stage.

19. The method of claim 11 , further comprising:

receiving, by a second amplifier from the second stage, a second residue voltage signal based on the second analog voltage signal and the second digital signal;

generating, by a third stage, a third stage ready signal;

receiving, by the second amplifier from the third stage, the third stage ready signal indicating that the second stage is ready to process a third analog voltage signal;

in response to the third stage ready signal, generating, by the second amplifier, the third analog voltage signal based on the second residue voltage signal; and

converting, by the third stage, the third analog voltage signal to a third digital signal including a third portion of the digital output signal.

20. The method of claim 11 , further comprising:

receiving, from the first stage, a first stage end signal indicating that the first stage completes processing the first analog voltage signal; and

generating the first amplifier start signal based on the second stage ready signal and the first stage end signal.