Circuit for and method of measuring latency in an integrated circuit
A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.
1. A circuit for measuring latency in an integrated circuit device, the circuit comprising:
a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and
a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit;
wherein the latency calculation circuit generates a latency value based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.
2. The circuit of claim 1 further comprising a transmission line coupled between the transmitter circuit and the latency calculation circuit, wherein the transmission line is within the integrated circuit device.
3. The circuit of claim 1 further comprising a transmission line coupled between the transmitter circuit and the latency calculation circuit, wherein the transmission line is external to the integrated circuit device.
4. The circuit of claim 1 wherein transmitter circuit further comprises an injector circuit configured to inject the marker representing the marker of the test signal.
5. The circuit of claim 1 wherein the signal generator comprises a pseudorandom binary sequence (PRBS) generator.
6. The circuit of claim 1 wherein further comprising a transmitter counter coupled to receive a start signal from the signal generator and a receiver counter coupled to receive a stop signal.
7. The circuit of claim 1 further comprising a skew measurement circuit configured to generate a clock skew value that compensates for the clock skew between a transmitter clock and a receiver clock.
8. A circuit for measuring latency in an integrated circuit device, the circuit comprising:
a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and
a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a skew measurement circuit;
wherein the latency calculation circuit generates a latency value based upon a latency count from the latency adjustment circuit and a clock skew from the skew measurement circuit.
9. The circuit of claim 8 further comprising a transmission line coupled between the transmitter circuit and the latency calculation circuit, wherein the transmission line is within the integrated circuit device.
10. The circuit of claim 8 further comprising a transmission line coupled between the transmitter circuit and the latency calculation circuit, wherein the transmission line is external to the integrated circuit device.
11. The circuit of claim 8 wherein transmitter circuit further comprises an injector circuit configured to inject a marker representing the marker of the test signal.
12. The circuit of claim 8 wherein the signal generator comprises a pseudorandom binary sequence (PRBS) generator.
13. The circuit of claim 8 wherein further comprising a transmitter counter coupled to receive a start signal from the signal generator and a receiver counter coupled to receive a stop signal.
14. The circuit of claim 8 further comprising an adder circuit configured to receive the latency count and the clock skew.
15. A method of measuring latency in an integrated circuit device, the method comprising:
transmitting a test signal having a marker for determining the latency in a path in the integrated circuit device;
receiving the test signal having a marker at a latency calculation circuit;
determining a latency count associated with the transmission of the test signal from a transmitter circuit to the latency calculation circuit as a course latency value;
determining a fine adjustment associated with the transmission of the test signal from the transmitter circuit to the latency calculation circuit; and
generating a latency value based upon the latency adjustment and the fine adjustment.
16. The method of claim 15 further comprising routing the test signal from the transmitter circuit to the latency calculation circuit within the integrated circuit device.
17. The method of claim 15 further comprising routing the test signal from the transmitter circuit to the latency calculation circuit by way of a transmission line external to the integrated circuit device.
18. The method of claim 15 further comprising injecting a marker representing the marker into a generated signal.
19. The method of claim 15 wherein transmitting a test signal comprises generating a pseudorandom binary sequence (PRBS) signal.
20. The method of claim 15 wherein the fine adjustment comprises at least one of a unit interval (UI) adjustment and a clock skew.