IP Library Granted Patent US 10,034,366
Granted Patent B2
US 10,034,366 · App. 15/792,953 · Granted Jul 24, 2018

Mating backplane for high speed, high density electrical connector

Inventors: Mark W. Gailus (Concord, MA); Marc B. Cartier, Jr. (Dover, NH); Vysakh Sivarajan (Nashua, NH); David Levine (Amherst, NH)
Assignee: Amphenol Corporation
H05K1/0222H01R43/205H05K1/025H05K1/0216H05K1/0219H05K1/0251H05K1/0298H05K1/115H05K3/0047H05K3/4038H05K2201/07H05K2201/09318H05K2201/09545
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Quick Facts
Patent No.
US 10,034,366
App. No.
15/792,953
Granted
Jul 24, 2018
Kind
B2
Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

Claims (35)

1. A printed circuit board comprising:

a plurality of layers including attachment layers and routing layers; and

via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:

first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers;

ground vias extending through at least the attachment layers; and

shadow vias located adjacent to each of the signal vias and extending through the attachment layers, the shadow vias being free of conductive material in the attachment layers.

2. The printed circuit board as defined in claim 1 , wherein the shadow vias extend through the attachment layers and the routing layers.

3. The printed circuit board as defined in claim 2 , wherein the shadow vias include conductive material in the routing layers.

4. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on opposite sides of the first and second signal vias.

5. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on a line through the first and second signal vias.

6. The printed circuit board as defined in claim 1 , wherein ground planes of the attachment layers are removed around the first and second signal vias to form antipads.

7. The printed circuit board as defined in claim 6 , wherein the shadow vias are located at edges of the antipads.

8. The printed circuit board as defined in claim 1 , wherein the shadow vias are located on opposite sides of the first and second signal vias and wherein additional shadow vias are located on a line through the first and second signal vias.

9. The printed circuit board as defined in claim 3 , wherein the first and second signal vias are configured to accept contact tails of signal conductors of a connector and wherein the ground vias are configured to accept contact tails of ground conductors of the connector.

10. A printed circuit board comprising:

a plurality of layers including attachment layers and routing layers; and

via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:

first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers;

ground vias extending through at least the attachment layers; and

ground shadow vias located adjacent to each of the signal vias and extending through the attachment layers, the ground shadow vias including ground shadow conductors that interconnect ground planes of two or more of the attachment layers.

11. The printed circuit board as defined in claim 10 , wherein the ground shadow vias extend through the attachment layers and the routing layers.

12. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are plated or filled with conductive material at least in the attachment layers.

13. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on opposite sides of the first and second signal vias.

14. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on a line through the first and second signal vias.

15. The printed circuit board as defined in claim 10 , wherein ground planes of the attachment layers are removed around the first and second signal vias to form antipads.

16. The printed circuit board as defined in claim 15 , wherein the ground shadow vias are located at edges of the antipads.

17. The printed circuit board as defined in claim 10 , wherein the ground shadow vias are located on opposite sides of the first and second signal vias and wherein additional ground shadow vias are located on a line through the first and second signal vias.

18. A printed circuit board comprising:

a plurality of layers including conductive layers separated by dielectric layers; and

via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:

first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers and connecting to respective signal traces on a breakout layer of the plurality of layers;

ground vias extending through one or more of the plurality of layers; and

shadow vias located adjacent to each of the signal vias and extending through one or more of the plurality of layers.

19. The printed circuit board as defined in claim 18 , wherein the shadow vias are free of conductive material at least in the layers above the breakout layer.

20. The printed circuit board as defined in claim 18 , wherein the ground shadow vias include ground shadow conductors that interconnect ground planes of two or more of the plurality of layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2018
From: GAILUS, MARK W.; CARTIER, MARC B., JR.; SIVARAJAN, VYSAKH; LEVINE, DAVID
To: AMPHENOL CORPORATION
Reel/Frame 044912/0977 →
Continuity (6)
Continuation 14947166 · Nov 20, 2015
Provisional Application 62190590 · Jul 9, 2015
Provisional Application 62172849 · Jun 9, 2015
Provisional Application 62172854 · Jun 9, 2015
Provisional Application 62082905 · Nov 21, 2014
Related Publication 20180049312A1 · Feb 15, 2018
Cited By (7)
US 1,067,191 US 1,068,685 US 12,207,395 US 12,300,942 US 12,309,915 US 12,444,863 US 12,720,680