IP Library › Granted Patent US 10,042,751
Granted Patent B1
US 10,042,751 · App. 14/871,344 · Granted Aug 7, 2018

Method and system for multi-tier all-flash array

Inventors: Alexandr Veprinsky (Brookline, MA); Assaf Natanzon (Tel Aviv, IL); Saar Cohen (Moshav, IL); Arieh Don (Newton, MA)
Assignee: EMC IP Holding Company LLC
G06F12/023G06F13/28G06F2212/251
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Quick Facts
Patent No.
US 10,042,751
App. No.
14/871,344
Filed
Sep 30, 2015
Granted
Aug 7, 2018
Kind
B1
Art Unit
2137
USPC
711/171
Abstract

Example embodiments of the present invention relate to a method, a system, and a computer program product for tiering metadata. The method includes selecting a consecutive range of addresses of a logical device having a parent data structure associated therewith maintaining a first set of hash values at a first granularity of the logical device. A second hash value then may be calculated over the consecutive range of addresses of the logical device at a second granularity of the logical device and inserted into a child data structure associated with the parent data structure. Entries in the parent data structure at the first granularity for the consecutive range of addresses then may be freed in favor of the second hash value at the second granularity for the consecutive range of addresses inserted into the child data structure, for storing hash values for other addresses of the logical device.

Claims (52)

1. A method comprising:

selecting a consecutive range of addresses of a logical device having a parent data structure associated therewith maintaining a first set of hash values comprising and corresponding to addresses of memory at a first granularity of the logical device, wherein the first set of hash values is generated from contents of the consecutive range of address;

inserting into a child data structure associated with the parent data structure a second hash value calculated over the consecutive range of addresses of the logical device comprising and corresponding to addresses of memory at a second granularity of the logical device, wherein the child data structure requires less storage space than the parent data structure; and

freeing entries in the parent data structure at the first granularity for the consecutive range of addresses, in favor of the second hash value at the second granularity for the consecutive range of addresses inserted into the child data structure, for storing hash values for other addresses of the logical device.

2. The method of claim 1 further comprising maintaining metadata in memory for the logical device according to the parent data structure maintaining the first set of hash values at the first granularity of the logical device and according to the child data structure into which was inserted the second hash value at the second granularity of the logical device.

3. The method of claim 2 further comprising performing inline deduplication over the logical device at both the first granularity and the second granularity.

4. The method of claim 3 wherein performing inline deduplication over the logical device at both the first granularity and the second granularity comprises:

performing a first inline deduplication of a first portion of the logical device according to the first set of hash values for the logical device in the parent data structure at the first granularity; and

performing a second inline deduplication of a second portion of the logical device according to the second hash value for the logical device in the child data structure at the second granularity.

5. The method of claim 1 further comprising serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity.

6. The method of claim 5 wherein serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity comprises, for a write I/O to the logical device:

writing data of the write I/O to its target address; and

writing a hash value for the write I/O to the parent data structure associated with the logical device.

7. The method of claim 5 wherein serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity comprises, for a read I/O to an address of the logical device:

attempting a first read of a hash value associated with the address from the parent data structure at the first granularity;

if the first read succeeds, returning the read hash value from the parent data structure at the first granularity;

if the first read fails, attempting a second read of the hash value associated with the address from the child data structure at the second granularity;

if the second read succeeds, returning the read hash value from the child data structure at the second granularity; and

if the second read fails, return a status.

8. The method of claim 7 further comprising using the read hash value as an index into a third data structure to identify a location of data satisfying the I/O on physical disks.

9. The method of claim 1 wherein selecting a consecutive range of addresses of a logical device having a parent data structure associated therewith maintaining a first set of hash values at a first granularity of the logical device comprises selecting the consecutive range of addresses according to a heat map identifying a frequency of access for each address.

10. The method of claim 9 further comprising tiering storage of the logical device by migrating data associated with the consecutive range of addresses from a first storage tier to a second storage tier.

11. A system comprising:

a processor;

a storage array;

a logical device stored on one or more storage devices on the storage array; and

computer program code that when executed on the processor performs the operations of:

selecting a consecutive range of addresses of the logical device having a parent data structure associated therewith maintaining a first set of hash values comprising and corresponding to addresses of memory at a first granularity of the logical device, wherein the first set of hash values is generated from contents of the consecutive range of address;

inserting into a child data structure associated with the parent data structure a second hash value calculated over the consecutive range of addresses comprising and corresponding to addresses of memory of the logical device at a second granularity of the logical device; and

freeing entries in the parent data structure at the first granularity for the consecutive range of addresses, in favor of the second hash value at the second granularity for the consecutive range of addresses inserted into the child data structure, for storing hash values for other addresses of the logical device, wherein the child data structure requires less storage space than the parent data structure.

12. The system of claim 11 further comprising maintaining metadata in memory for the logical device according to the parent data structure maintaining the first set of hash values at the first granularity of the logical device and according to the child data structure into which was inserted the second hash value at the second granularity of the logical device.

13. The system of claim 12 further comprising performing inline deduplication over the logical device at both the first granularity and the second granularity.

14. The system of claim 13 wherein performing inline deduplication over the logical device at both the first granularity and the second granularity comprises:

performing a first inline deduplication of a first portion of the logical device according to the first set of hash values for the logical device in the parent data structure at the first granularity; and

performing a second inline deduplication of a second portion of the logical device according to the second hash value for the logical device in the child data structure at the second granularity.

15. The system of claim 11 further comprising serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity.

16. The system of claim 15 wherein serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity comprises, for a write I/O to the logical device:

writing data of the write I/O to its target address; and

writing a hash value for the write I/O to the parent data structure associated with the logical device.

17. The system of claim 15 wherein serving Input/Output (I/O) to the logical device according to the parent data structure at the first granularity and according to the child data structure at the second granularity comprises, for a read I/O to an address of the logical device:

attempting a first read of a hash value associated with the address from the child data structure at the second granularity;

if the first read succeeds, returning the read hash value from the child data structure at the second granularity;

if the first read fails, attempting a second read of the hash value associated with the address from the parent data structure at the first granularity;

if the second read succeeds, returning the read hash value from the parent data structure at the first granularity; and

if the second read fails, failing the read I/O.

18. The system of claim 17 further comprising using the read hash value as an index into a third data structure to identify a location of data satisfying the I/O on physical disks.

19. The system of claim 11 wherein selecting a consecutive range of addresses of a logical device having a parent data structure associated therewith maintaining a first set of hash values at a first granularity of the logical device comprises selecting the consecutive range of addresses according to a heat map identifying a frequency of access for each address.

20. The system of claim 19 further comprising tiering storage of the logical device by migrating data associated with the consecutive range of addresses from a first storage tier to a second storage tier.

21. A computer program product having computer executable code embodied in non-transitory storage media comprising:

computer program code for selecting a consecutive range of addresses of a logical device having a parent data structure associated therewith maintaining a first set of hash values comprising and corresponding to addresses of memory at a first granularity of the logical device, wherein the first set of hash values is generated from contents of the consecutive range of address;

computer program code for inserting into a child data structure associated with the parent data structure a second hash value calculated over the consecutive range of addresses comprising and corresponding to addresses of memory of the logical device at a second granularity of the logical device; and

computer program code for freeing entries in the parent data structure at the first granularity for the consecutive range of addresses, in favor of the second hash value at the second granularity for the consecutive range of addresses inserted into the child data structure, for storing hash values for other addresses of the logical device, wherein the child data structure requires less storage space than the parent data structure.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2016
From: VEPRINSKY, ALEXANDR; NATANZON, ASSAF; COHEN, SAAR; DON, ARIEH
To: EMC CORPORATION
Reel/Frame 037658/0684 →
Cited By (3)
US 12,216,929 US 12,277,054 US 12,585,541