Stacked image sensor pixel cell with selectable shutter modes and in-pixel CDS
A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor and a readout circuit block. The photodiode, transfer transistor, reset transistor and amplifier transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode and converting the image charge to an image signal. The readout circuit block is disposed within a second substrate of a second semiconductor chip and the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.
1. A pixel cell, comprising:
a first substrate having a front surface and a back surface;
a set of transfer transistors, each coupled to respective photodiodes and sharing floating drains, disposed within the first substrate for accumulating and transferring an image charge in response to light incident upon the photodiodes;
a reset transistor and an amplifier transistor disposed within the first substrate for converting the image charge to an image signal for coupling out of the first substrate;
a readout circuit block disposed within a second substrate stacked upon the front surface of the first substrate, wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes, wherein the optionally selectable rolling shutter mode of the readout circuit block causes the image signal from the amplifier transistor to couple through a rolling shutter select transistor to a column line of an image sensor while other transistors within the readout circuit block are turned off, and wherein the selectable global shutter mode of the readout circuit block causes the image signal from the amplifier transistor to couple through a global shutter select transistor to a column line of an image sensor while a rolling shutter select transistor within the readout circuit block is turned off, and wherein an output terminal of the rolling shutter select transistor is directly connected to an output terminal of the global shutter select transistor; and
inter-chip electrical interconnects which directly couple the amplifier transistor to the readout circuit block.
2. The pixel cell of claim 1 , wherein the set of transfer transistors and respective photodiodes comprises four transistors and four photodiodes, wherein all the transfer transistors share a floating drain coupled to the reset transistor and the amplifier transistor.
3. The pixel cell of claim 2 , wherein the four photodiodes are arranged in a two by two block.
4. The pixel cell of claim 2 , wherein one of the photodiodes receives incident light through a red filter and one other of the photodiodes receives incident light through a blue filter and two other of the photodiodes receives incident light through green filters.
5. The pixel cell of claim 1 , wherein the selected readout mode is determined by the status of a selectable state register setting within an image sensor.
6. The pixel cell of claim 1 , wherein the global shutter mode of the readout circuit block includes circuit elements coupled between the amplifier transistor and a global shutter output amplifier transistor that are operable to perform correlated double sampling (CDS) on the amplifier transistor and the circuit elements.
7. The pixel cell of claim 6 , wherein between an input to the global shutter output amplifier and a ground connection there are three components, wherein a reset capacitor (Crst) is coupled between the input to the global shutter output amplifier and a terminal coupled to the image signal and wherein a signal capacitor (Csig) is coupled between the terminal and drain of a global signal select transistor wherein the source of the global signal select transistor is coupled to the ground connection.
8. The pixel cell of claim 7 , wherein a global shutter reset transistor couples the image signal amplifier transistor to the terminal between the reset capacitor and the signal capacitor, and wherein a global shutter bias current transistor couples the image signal amplifier to the ground connection.
9. The pixel cell of claim 7 , wherein the optionally selectable global shutter mode of the readout circuit block causes the image signal from the global shutter output amplifier to couple through a global shutter select transistor to a column line of an image sensor while a rolling shutter select transistor is turned off.
10. The pixel cell of claim 6 , wherein between an input to the global shutter output amplifier and a ground connection there are three components, wherein a reset capacitor (Crst) is coupled between the input to the global shutter output amplifier and the drain of a global signal select transistor wherein the source of the global signal select transistor is coupled to a terminal coupled to the image signal and wherein a signal capacitor (Csig) is coupled between the terminal and the ground connection.
11. The pixel cell of claim 10 , wherein a global shutter reset transistor couples the image signal amplifier transistor to the terminal between the source of the global signal select transistor and the signal capacitor and wherein a global shutter bias current transistor couples the image signal amplifier to the ground connection.
12. The pixel cell of claim 1 whereby one inter-chip interconnect couples the amplifier transistor drain to a power supply.
13. An imaging system component of a digital camera, the imaging system comprising:
a plurality of pixel cells arranged in a two-dimensional array, each of the pixel cells comprising: a first substrate having a front surface, and a back surface;
a set of transfer transistors, each coupled to respective photodiodes and sharing floating drains, disposed within the first substrate for accumulating and transferring an image charge in response to light incident upon the photodiodes;
a reset transistor and an amplifier transistor disposed within the first substrate for converting the image charge to an image signal for coupling out of the first substrate;
a readout circuit block disposed within a second substrate stacked upon the front surface of the first substrate, wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes, wherein the optionally selectable rolling shutter mode of the readout circuit block causes the image signal from the amplifier transistor to couple through a rolling shutter select transistor to a column line of an image sensor while other transistors within the readout circuit block are turned off, and wherein the selectable global shutter mode of the readout circuit block causes the image signal from the amplifier transistor to couple through a global shutter select transistor to a column line of an image sensor while a rolling shutter select transistor within the readout circuit block is turned off, and wherein an output terminal of the rolling shutter select transistor is directly connected to an output terminal of the global shutter select transistor; and
inter-chip electrical interconnects which directly couple the amplifier transistor to the readout circuit block.