IP Library Granted Patent US 10,073,138
Granted Patent B2
US 10,073,138 · App. 14/979,301 · Granted Sep 11, 2018

Early detection of reliability degradation through analysis of multiple physically unclonable function circuit codes

Inventors: Suraj Sindia (Hillsboro, OR); Robert Kwasnick (Palo Alto, CA); Dhruv Singh (Hillsboro, OR)
Assignee: Intel Corporation
G01R31/31703G01R31/3177H04L9/0866H04L9/0891H04L9/3278H04L2209/34
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Quick Facts
Patent No.
US 10,073,138
App. No.
14/979,301
Granted
Sep 11, 2018
Kind
B2
Abstract

An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.

Claims (37)

1. An apparatus, comprising:

a plurality of circuits each designed to exhibit a unique signature code that is dependent on parameters of a manufacturing process used to manufacture the plurality of circuits;

entropy determination circuitry to determine a potential reliability problem has arisen based on a change in signature codes from the plurality of circuits characterized by high entropy amongst the signature codes during normal drift of the parameters owing to degradation of the plurality of circuits to low entropy amongst the signature codes owing to a significant change in at least one of the parameters, wherein, the high entropy amongst the signature codes is characterized by a larger disparity in different signature codes than the low entropy amongst the signature codes.

2. The apparatus of claim 1 further comprising a memory to store the signature codes.

3. The apparatus of claim 2 wherein the memory is a nonvolatile memory.

4. The apparatus of claim 2 wherein the memory is coupled to the error circuitry.

5. The apparatus of claim 1 wherein the plurality of circuits and the entropy determination circuitry are implemented on a semiconductor chip.

6. The apparatus of claim 1 wherein the plurality of circuits and the entropy determination circuitry are implemented on a printed circuit board.

7. The apparatus of claim 1 wherein the entropy determination circuitry is implemented with any one or more of:

custom designed circuitry;

programmable logic circuitry;

program code.

8. A computing system, comprising:

one or more processing cores;

a memory controller coupled to the one or more processing cores; a system memory coupled to the memory controller;

a display;

a network interface;

a plurality of circuits each designed to exhibit a unique signature code that is dependent on parameters of a manufacturing process used to manufacture the plurality of circuits; and,

entropy determination circuitry to determine a potential reliability problem has arisen based on a change in signature codes from the plurality of circuits characterized by high entropy amongst the signature codes during normal drift of the parameters owing to degradation of the plurality of circuits to low entropy amongst the signature codes owing to a significant change in at least one of the parameters, wherein, the high entropy amongst the signature codes is characterized by a larger disparity in different signature codes than the low entropy amongst the signature codes.

9. The computing system of claim 8 further comprising a memory to store the signature codes.

10. The computing system of claim 9 wherein the memory is a nonvolatile memory.

11. The computing system of claim 9 wherein the memory is coupled to the error circuitry.

12. The computing system of claim 8 wherein the plurality of circuits and the entropy determination circuitry are implemented on a semiconductor chip.

13. The computing system of claim 8 wherein the plurality of circuits and the entropy determination circuitry are implemented on a printed circuit board.

14. The computing system of claim 8 wherein the entropy determination circuitry is implemented with any one or more of:

custom designed circuitry;

programmable logic circuitry;

program code.

15. A non-transitory machine readable storage medium containing program code that when processed by a processor causes a method to be performed, wherein the method comprises:

receiving signature codes from a plurality of circuits where the signature codes are dependent on parameters of the manufacturing process used to manufacture the plurality of circuits; and,

determining whether an error exists based on an entropy analysis of the signature codes characterized by high entropy amongst the signature codes during normal drift of the parameters owing to degradation of the plurality of circuits to low entropy amongst the signature codes owing to a significant change in at least one of the parameters, wherein, the high entropy amongst the signature codes is characterized by a larger disparity in different signature codes than the low entropy amongst the signature codes.

16. The machine readable medium of claim 15 wherein the determining includes comparing the signature codes against earlier versions of the signature codes.

17. The machine readable medium of claim 15 wherein the determining includes determining an entropy of the signature codes.

18. The machine readable medium of claim 15 wherein the plurality of circuits are manufactured on any of:

a semiconductor

chip; a printed circuit

board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: SINDIA, SURAJ; KWASNICK, ROBERT F.; SINGH, DHRUV
To: INTEL CORPORATION
Reel/Frame 037670/0078 →
Continuity (1)
Related Publication 20170176527A1 · Jun 22, 2017