IP Library Granted Patent US 10,074,620
Granted Patent B2
US 10,074,620 · App. 15/013,858 · Granted Sep 11, 2018

Semiconductor package with integrated output inductor using conductive clips

Inventors: Eung San Cho (Torrance, CA); Darryl Galipeau (Warwick, RI); Dan Clavette (Greene, RI)
Assignee: Infineon Technologies Americas Corp.
H01L23/645H01F17/0033H01L23/495H01L23/49537H01L23/49562H01L24/49H01L23/3121H01L24/32H01L24/45H01L24/48H01L24/73H01L2224/32245H01L2224/45014H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/48247H01L2224/48257H01L2224/49171H01L2224/73265H01L2924/00011H01L2924/1032H01L2924/1033H01L2924/10253H01L2924/13055H01L2924/13064H01L2924/13091H01L2924/14H01L2924/181H01L2924/19042H02M3/158
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Quick Facts
Patent No.
US 10,074,620
App. No.
15/013,858
Granted
Sep 11, 2018
Kind
B2
Abstract

A semiconductor package includes a semiconductor die having a control transistor and a sync transistor, an integrated output inductor having a winding around a core, and coupled to the semiconductor die, where the winding includes a plurality of top conductive clips connected to a plurality of bottom conductive clips. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of top conductive clips and the plurality of bottom conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Claims (26)

1. A semiconductor package comprising:

a semiconductor die comprising a control transistor and a sync transistor;

an integrated output inductor comprising a winding around a core, and coupled to said semiconductor die;

wherein said winding comprises a plurality of top conductive clips connected to a plurality of bottom conductive clips.

2. The semiconductor package of claim 1 wherein said control transistor and said sync transistor are configured as a half-bridge.

3. The semiconductor package of claim 2 wherein said integrated output inductor is coupled to a switched node of said half-bridge.

4. The semiconductor package of claim 1 wherein at least one of said plurality of top conductive clips and said plurality of bottom conductive clips includes a partially etched portion and a non-etched portion.

5. The semiconductor package of claim 1 wherein said semiconductor die further comprises a driver integrated circuit coupled to said control transistor and said sync transistor.

6. The semiconductor package of claim 1 wherein at least one of said control transistor and said sync transistor comprises a group III-V transistor.

7. The semiconductor package of claim 1 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

8. The semiconductor package of claim 1 wherein said core is a ferrite core.

9. The semiconductor package of claim 1 wherein said semiconductor die is attached to said integrated output inductor by a die attach material.

10. The semiconductor package of claim 1 wherein said semiconductor die and said integrated output inductor are encapsulated in a molding compound.

11. A semiconductor package comprising:

an integrated output inductor comprising a winding around a core;

a power stage stacked over said integrated output inductor, said power stage comprising a control transistor and a sync transistor connected in a half-bridge;

wherein said winding comprises a plurality of top conductive clips connected to a plurality of bottom conductive clips.

12. The semiconductor package of claim 11 wherein at least one of said plurality of top conductive clips and said plurality of bottom conductive clips includes a partially etched portion and a non-etched portion.

13. The semiconductor package of claim 11 wherein said integrated output inductor is coupled to a switched node of said half-bridge.

14. The semiconductor package of claim 11 wherein said power stage further comprises a driver integrated circuit coupled to said control transistor and said sync transistor.

15. The semiconductor package of claim 11 wherein said core is a ferrite core.

16. The semiconductor package of claim 11 wherein at least one of said control transistor and said sync transistor comprises a group III-V transistor.

17. The semiconductor package of claim 11 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

18. The semiconductor package of claim 11 wherein said control transistor and said sync transistor are monolithically integrated on a semiconductor die.

19. The semiconductor package of claim 18 wherein said semiconductor die is attached to said integrated output inductor by a die attach material.

20. The semiconductor package of claim 11 wherein said power stage and said integrated output inductor are encapsulated in a molding compound.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2016
From: CHO, EUNG SAN; GALIPEAU, DARRYL; CLAVETTE, DAN
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 037649/0939 →
Continuity (2)
Provisional Application 62137967 · Mar 25, 2015
Related Publication 20160286656A1 · Sep 29, 2016