IP Library Granted Patent US 10,079,295
Granted Patent B2
US 10,079,295 · App. 14/629,575 · Granted Sep 18, 2018

Semiconductor device and method for manufacturing thereof

Inventors: Atsuo Isobe (Isehara, JP); Toshinari Sasaki (Tochigi, JP); Shinya Sasagawa (Chigasaki, JP); Akihiro Ishizuka (Sagamihara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L27/0688H01L27/1225H01L29/42384H01L29/7869H01L29/78603H01L29/78642H01L29/78696H01L21/02554H01L21/02565H01L21/02667
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Quick Facts
Patent No.
US 10,079,295
App. No.
14/629,575
Granted
Sep 18, 2018
Kind
B2
Abstract

A method for manufacturing an oxide semiconductor layer, comprising forming an oxide semiconductor layer over an insulating layer so as to be along with a curved surface of a projecting structural body of the insulating layer, wherein a length of the projecting structural body in a height direction is larger than a width of the projecting structural body, is provided.

Claims (43)

1. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer over a substrate, the insulating layer including a projecting structural body that includes a curved surface in an upper end corner portion where a top surface of the projecting structural body and a side surface of the projecting structural body intersect with each other;

forming an oxide semiconductor layer over the insulating layer, the oxide semiconductor layer having a c-axis parallel to a normal vector of a surface of the oxide semiconductor layer;

forming a source electrode and a drain electrode adjacent to the oxide semiconductor layer;

forming a gate insulating layer adjacent to the oxide semiconductor layer; and

forming a gate electrode adjacent to the gate insulating layer, wherein the gate insulating layer is interposed between a side surface of the oxide semiconductor layer and a side surface of the gate electrode; and

forming a bit line electrically connected to the oxide semiconductor layer through one of the source electrode and the drain electrode.

2. The method for manufacturing a semiconductor device, according to claim 1 ,

wherein the oxide semiconductor layer is in contact with at least a part of the top surface and the side surface of the projecting structural body,

wherein a heat treatment is performed at a temperature higher than or equal to 400° C., when forming the oxide semiconductor layer, and

wherein the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to the curved surface.

3. The method for manufacturing a semiconductor device, according to claim 1 ,

wherein plasma treatment is performed on the projecting structural body in a rare gas atmosphere to form the curved surface.

4. The method for manufacturing a semiconductor device, according to claim 3 , wherein the rare gas is argon.

5. The method for manufacturing a semiconductor device, according to claim 1 ,

wherein the projecting structural body is formed with the use of a metal mask, and

wherein the curved surface is formed, when the metal mask is removed by dry etching using a reactive gas.

6. The method for manufacturing a semiconductor device, according to claim 1 , wherein the curved surface has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

7. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer over a substrate, the insulating layer including a projecting structural body that includes a curved surface in an upper end corner portion where a top surface of the projecting structural body and a side surface of the projecting structural body intersect with each other;

forming an oxide semiconductor layer having an amorphous state in contact with at least a part of the top surface and the side surface while heat treatment is performed at a temperature lower than 200° C.;

heating the oxide semiconductor layer at a temperature higher than or equal to 450° C. wherein the heated oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to the curved surface;

forming a source electrode and a drain electrode adjacent to the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer to cover at least a part of the top surface and the side surface, wherein the gate insulating layer is interposed between a side surface of the oxide semiconductor layer and a side surface of the gate electrode; and

forming a bit line electrically connected to the oxide semiconductor layer through one of the source electrode and the drain electrode.

8. The method for manufacturing a semiconductor device, according to claim 7 ,

wherein plasma treatment is performed on the projecting structural body in a rare gas atmosphere to form the curved surface.

9. The method for manufacturing a semiconductor device, according to claim 8 , wherein the rare gas is argon.

10. The method for manufacturing a semiconductor device, according to claim 7 ,

wherein the projecting structural body is formed with the use of a metal mask, and

wherein the curved surface is formed, when the metal mask is removed by dry etching using a reactive gas.

11. The method for manufacturing a semiconductor device, according to claim 7 , wherein the curved surface has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

12. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer including a projecting structural body and a substrate;

forming an oxide semiconductor region over the insulating layer, the oxide semiconductor region having a c-axis parallel to a normal vector of a surface of the oxide semiconductor region;

forming an insulating region;

forming a first conductive region functioning as a word line, wherein the insulating region is interposed between a side surface of the oxide semiconductor region and a side surface of first conductive region; and

forming a second conductive region functioning as a bit line, wherein the second conductive region is electrically connected to the oxide semiconductor region,

wherein the oxide semiconductor region comprises a channel formation region.

13. The method for manufacturing a semiconductor device according to claim 12 , wherein the channel formation region is extended in a three dimensional direction.

14. The method for manufacturing a semiconductor device according to claim 12 , wherein the oxide semiconductor region comprises indium, gallium, and zinc.

15. The method for manufacturing a semiconductor device according to claim 12 , wherein a memory comprises the oxide semiconductor region, the insulating region, the first conductive region, and the second conductive region.

Priority Claims (1)
JP 2011-096298 · Apr 22, 2011 · national
Continuity (2)
Division 13446028 · Apr 13, 2012
Related Publication 20150179776A1 · Jun 25, 2015
Cited By (2)
US 12,382,664 US 12,402,360