Random access to signal values of an FPGA at runtime
View Patent ↗A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.
1. A method for making an FPGA build, based on an FPGA model, using a hardware description language, the method comprising:
creating an FPGA hardware configuration;
identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration;
creating a list with signal values accessible at runtime and the memory locations corresponding thereto;
converting the created list into a machine-readable FPGA variable mapping file for accessing the signal values at the memory locations during operation.
2. The method according to claim 1 , wherein the step of creating a list with readable signal values and the memory locations corresponding thereto comprises identifying a linking of the memory locations for the formation of the signal value.
3. The method according to claim 1 , further comprising generating an FPGA code for determining a signal value, wherein the FPGA code comprises reading the status data from the configuration memory as readback data and determining the signal value from the readback data based on the list with readable signal values and the memory locations corresponding thereto.
4. The method according to claim 1 , further comprising optimizing the FPGA hardware configuration with an arrangement of memory locations containing the status data for a signal value in a readback column of the FPGA.
5. The method according to claim 1 , further comprising optimizing the FPGA hardware configuration with an arrangement of memory locations containing states for a signal value in adjacent areas of the FPGA.
6. The method according to claim 1 , further comprising adding memory locations at outputs of logic blocks for providing status data.