IP Library Granted Patent US 10,083,138
Granted Patent B2
US 10,083,138 · App. 15/053,095 · Granted Sep 25, 2018

Controller, bus circuit, control method, and recording medium

Inventor: Shinya Oda (Tokyo, JP)
Assignee: NEC CORPORATION
G06F13/364G06F13/404G06F13/4282
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Quick Facts
Patent No.
US 10,083,138
App. No.
15/053,095
Granted
Sep 25, 2018
Kind
B2
Abstract

A controller includes a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an instruction input to the target device and a response to the instruction input, predicting a response of the target device to the instruction acquired, and outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and a master circuit connected to the target device with the bus, the master circuit transmitting the instruction to the target device through the bus, and performing initial setting of the target device based on the fault report from the pseudo device circuit.

Claims (29)

1. A controller comprising:

a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an instruction input to the target device and a response to the instruction input, predicting a response of the target device to the instruction acquired, and outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and

a master circuit connected to the target device with the bus, the master circuit transmitting the instruction to the target device through the bus, and performing initial setting of the target device based on the fault report from the pseudo device circuit.

2. The controller according to claim 1 , wherein the pseudo device circuit detects the difference between a predicted response and an acquired response, based on a determination as to whether the acquired response is a normal response or an abnormal response or a data value that included in the acquired response falls within a predetermined range or not.

3. A bus circuit comprising: the controller according to claim 2 ;

a target device; and

a bus connecting the controller and the target device.

4. A bus circuit comprising: the controller according to claim 1 ;

a target device; and

a bus connecting the controller and the target device.

5. The bus circuit according to claim 4 further comprising:

a non-target device connected to the bus,

wherein the master circuit transmits a command of the target device and a command of the non-target device, and resets the target device, the non-target device and the bus to perform initial setting when detecting bus lock of the bus.

6. The bus circuit according to claim 5 , wherein

the master circuit transmits the instruction including an address of the target device or the non-target device,

the target device performs a predetermined operation when the instruction received includes an address of own device, and

the pseudo device circuit predicts the predicted response when the instruction acquired includes an address of the target device.

7. A control method of a controller connected to a target device with a bus and a reset line, the control method comprising:

acquiring from the bus an instruction input to the target device and a response to the instruction input;

predicting a response of the target device to the instruction acquired; and

outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and

performing initial setting of the target device based on the fault report from the pseudo device circuit.

8. The control method of the controller according to claim 7 , wherein the difference between the predicted response and the acquired response is detected, based on a determination as to whether the acquired response is a normal response or an abnormal response or a data value that included in the acquired response falls within a predetermined range or not.

9. A non-transitory computer-readable medium storing a program which causes a computer connected to a target device with a bus and a reset line to:

acquire from the bus an instruction input to the target device and a response to the instruction input;

predict a response of the target device to the instruction acquired; and

output a fault report when a difference is detected between a predicted response and an acquired response, and output a reset signal to the reset line; and

perform initial setting of the target device based on the fault report from the pseudo device circuit.

10. The computer-readable medium according to claim 9 , wherein a program is stored which causes to perform detecting a difference between a predicted response and an acquired response based on a determination as to whether the acquired response is a normal response or an abnormal response or a data value that included in the acquired response falls within a predetermined range or not.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2016
From: ODA, SHINYA
To: NEC CORPORATION
Reel/Frame 037827/0074 →
Priority Claims (1)
JP 2015-045486 · Mar 9, 2015 · national
Continuity (1)
Related Publication 20160267034A1 · Sep 15, 2016