Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts

1. A vertical SRAM cell comprising:

a first (1 st ) inverter having a 1 st common gate structure operatively connecting channels of a 1 st pull-up (PU) and a 1 st pull-down (PD) transistor, and a 1 st metal contact electrically connecting bottom source/drain (S/D) regions of the 1 st PU and 1 st PD transistors;

a second (2 nd ) inverter having a 2 nd common gate structure operatively connecting channels of a 2 nd PU and a 2 nd PD transistor, and a 2 nd metal contact electrically connecting bottom S/D regions of the 2 nd PU and 2 nd PD transistors;

a 1 st cross-coupled contact electrically connecting the 2 nd common gate structure to the 1 st metal contact, the 2 nd common gate structure entirely surrounding a perimeter of the 1 st cross-coupled contact; and

a 2 nd cross-coupled contact electrically connecting the 1 st common gate structure to the 2 nd metal contact, the 1 st common gate structure entirely surrounding a perimeter of the 2 nd cross-coupled contact.

2. The vertical SRAM cell of claim 1 comprising:

the 1 st cross-coupled contact penetrating the 2 nd common gate structure such that the 1 st cross-coupled contact does not extend between edges of the 1 st and 2 nd common gate structures; and

the 2 nd cross-coupled contact penetrating the 1 st common gate structure such that the 2 nd cross-coupled contact does not extend between edges of the 1 st and 2 nd common gate structures.

3. The vertical SRAM cell of claim 1 comprising:

the 1 st and 2 nd common gate structures having a minimum pitch distance; and

the 1 st and 2 nd cross-coupled contacts having a minimum separation distance between edges of the cross-coupled contacts and edges of adjacent gate structures;

wherein the minimum separation distance is greater than or equal to the minimum pitch distance.

4. The vertical SRAM cell of claim 1 comprising:

the 1 st metal contact disposed on sidewalls, and not on a top surface, of the bottom S/D regions of the 1 st PU and 1 st PD transistors; and

the 2 nd metal contact disposed on sidewalls, and not on a top surface, of the bottom S/D regions of the 2 nd PU and 2 nd PD transistors.

5. The vertical SRAM cell of claim 1 comprising:

the bottom S/D regions of the 1 st PU, 1 st PD, 2 nd PU and 2 nd PD transistors being disposed on a substrate,

the channels of the 1 st PU, 1 st PD, 2 nd PU and 2 nd PD transistors extending upwards from a top surface of the bottom S/D regions,

the 1 st common gate structure disposed above the bottom S/D regions of the 1 st PU and the 1 st PD transistors; and

the 2 nd common gate structure disposed above the bottom S/D regions of the 2 nd PU and 2 nd PD transistors.

6. The vertical SRAM cell of claim 5 comprising:

each of the 1 st PU, 1 st PD, 2 nd PU and 2 nd PD transistors having:

an upper S/D region disposed on an upper end of each channel, and

a CA contact disposed on the upper S/D region, the CA contacts each having a lower surface disposed at a lower surface height above the substrate; and

an upper surface of each of the cross-coupled contacts disposed at a recessed height above the substrate;

wherein the lower surface height of the lower surface of the CA contacts is above a level of the recessed height of the upper surface of the cross-coupled contacts.

7. The vertical SRAM cell of claim 6 comprising:

each of the upper surfaces of the cross-coupled contacts having a 1 st width; and

a dielectric plug disposed over each of the upper surfaces of the cross-coupled contacts, each dielectric plug having a 2 nd width;

wherein the 2 nd width is larger than the 1 st width.

8. The vertical SRAM cell of claim 7 comprising:

each dielectric plug having sidewalls; and

each CA contact being self-aligned with at least one sidewall of the dielectric plugs.

9. The vertical SRAM cell of claim 6 comprising:

the 1 st and 2 nd common gate structures having an upper surface at an upper surface height and a lower surface at a lower surface height;

wherein the recessed height of the upper surface of the cross-coupled contacts is above the lower surface height of the lower surface of the common gate structures; and

wherein the recessed height of the upper surface of the cross-coupled contacts is below the upper surface height of the upper surface of the common gate structures.

10. The vertical SRAM cell of claim 5 comprising:

the 1 st metal contact, the 1 st cross-coupled contact, the bottom S/D region of the 1 st PU transistor, the bottom S/D region of the 1 st PD transistor and the 2 nd common gate structure being electrically connected to form a 1 st storage node; and

the 2 nd metal contact, the 2 nd cross-coupled contact, the bottom S/D region of the 2 nd PU transistor, the bottom S/D region of the 2 nd PD transistor and the 1 st common gate structure being electrically connected to form a 2 nd storage node.

11. The vertical SRAM cell of claim 10 comprising:

a 1 st pass-gate (PG) transistor having a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region;

a 2 nd PG transistor having a bottom S/D region disposed on the substrate and a channel extending vertically upwards from a top surface of the bottom S/D region;

wherein the bottom S/D region of the 1 st PG transistor is in electric contact with the Pt storage node; and

wherein the bottom S/D region of the 2 nd PG transistor is in electric contact with the 2 nd storage node.

12. The vertical SRAM cell of claim 11 comprising:

the bottom S/D regions of the 1 st PG and 1 st PD transistors being a single 1 st common bottom S/D region; and

the bottom S/D region of the 2 nd PG and 2 nd PD transistors being a single 2 nd common bottom S/D region.

13. The vertical SRAM cell of claim 11 comprising the channels of the 1 st PU, 1 st PD, 1 st PG, 2 nd PU, 2 nd PD and 2 nd PG transistors being one of a fin and a nanowire.

14. The vertical SRAM cell of claim 11 comprising:

the 1 st PU and 2 nd PU transistors being a p-type transistor;

the 1 st PD and 2 nd PD transistors being an n-type transistor; and

the 1 st PG and 2 nd PG transistors being an n-type transistor.

15. The vertical SRAM cell of claim 1 comprising:

the 1 st cross-coupled contact being disposed on at least one of the 1 st metal contact, the bottom S/D region of the 1 st PU transistor and the bottom S/D region of the 1 st PD transistor; and

the 2 nd cross-coupled contact being disposed on at least one of the 2 nd metal contact, the bottom S/D region of the 2 nd PU transistor and the bottom S/D region of the 2 nd PD transistor.