Mode switching for increased off-chip bandwidth

1. A method of increasing off-chip bandwidth, comprising:

designing a circuit having switchable pins;

replacing a portion of allocated pins of a processor with the switchable pins;

connecting the processor to a memory interface configured to dynamically switch the switchable pins between a power mode and a signal mode;

providing a metric configured to identify which of the power mode and the signal mode is most beneficial during a 1 millisecond interval;

switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode; and

utilizing an off-chip bus connection to switch from a multi-bus mode to a single-bus mode and vice-versa,

the circuit including

a first circuit having a signal-to-power switch and a first set of five stage tri-stage buffers connected to the signal-to-power switch, wherein the first set of five stage tri-stage buffers are placed in signal lines to amplify I/O signals to compensate for parasitic capacitances of the signal-to-power switch, and wherein the signal-to-power switch allows for the switchable pins to alternate between the multi-bus and single-bus mode;

a second circuit having a signal switch and a second set of five stage tri-stage buffers connected to the signal switch, wherein the second set of five stage tri-stage buffers enable memory devices that can be accessed via buses, and wherein the signal switch ensures that data in the memory interface can be accessed in the multi-bus and single-bus modes; and

a third circuit having a signal buffer that amplifies the I/O signals in order to offset effects of parasitic capacitance, and

wherein the signal-to-power switch and signal switch are configured to route signals and power in the multi-bus and single-bus modes.

2. The method of claim 1 , further comprising utilizing cache block prefetching techniques to amplify benefits of the switchable pins.

3. The method of claim 1 , further comprising allocating not more than three additional buses via pin switching.

4. The method of claim 1 , wherein the metric is switching benefit, B ij (T c ), wherein B ij (T c ) represents the estimated reward for running the interval following time T c in mode j instead of mode i.

5. The method of claim 3 , wherein the multi-bus mode includes N number of buses connected to private DRAM interfaces via individual buses and the single-bus mode includes a single bus connected to a private DRAM interface.

6. The method of claim 4 , wherein the switching benefit, B ij (T c ), is calculated using the following equation:

B ij ( T c )=Σ k=1 p ( WS j,k ( T c )− WS i,k ( T c )),

wherein WS i,k (T c ) and WS j,k (T c ) are estimated weighted speedups for program k at time T c in mode i and mode j respectively, and p is the number of simultaneously executing programs.

7. The method of claim 5 , further comprising using a memory controller to assist in switching between the multi-bus and single-bus modes.

8. The method of claim 6 , wherein based on a history of the switching benefit, B ij (T c ), {tilde over (B)} ij (T c ) is predicted as a switching benefit for a following interval using the equation: {tilde over (B)} ij (T c )=Σ k=1 N B ij (T c −k*T interval ),

wherein B ij (T c −k*T interval ) represents switching benefit, B ij (T c ), and is measured from N intervals ago.

9. The method of claim 7 , wherein the memory controller includes:

a front arbiter;

N dedicated request queues configured to individually receive incoming requests from the front arbiter;

an end arbiter that fetches requests residing in the queues,

wherein the requests are fed via corresponding DRAM interfaces into corresponding DIMMs while in the multi-bus mode,

wherein the requests are fed via a single DRAM interface into attached DIMMs as appended ranks while in the single-bus mode.

10. The method of claim 8 , wherein the method includes:

staying in mode i if the predicted switching benefit, {tilde over (B)} ij (T c ), is negative;

switching to mode j if the predicted switching benefit, {tilde over (B)} ij (T c ), is positive.

11. The method of claim 9 , further comprising employing XOR banking indexing to reduce row-buffer conflicts.

12. The method of claim 10 , wherein the weighted speedup is calculated using the following equation:

Weighted

⁢

⁢

Speedup

=

∑

i

=

0

n

-

1

⁢

⁢

1

/

T

i

Shared

1

/

T

i

Alone

wherein T i Shared and T i Alone denote an execution time of a single program running alone, and an execution time of a single program running with other programs, respectively.

13. The method of claim 11 , further comprising analyzing signal integrity to demonstrate feasibility in the multi-bus and single-bus modes.

14. A circuit, comprising:

switchable pins;

a first circuit having a signal-to-power switch and a first set of five stage tri-stage buffers connected to the signal-to-power switch, wherein the first set of five stage tri-stage buffers are placed in signal lines to amplify I/O signals to compensate for parasitic capacitances of the signal-to-power switch;

a second circuit having a signal switch and a second set of five stage tri-stage buffers connected to the signal switch, wherein the second set of five stage tri-stage buffers enable memory devices that can be accessed via buses; and

a third circuit having a signal buffer,

wherein the signal-to-power switch allows for the switchable pins to alternate between a multi-bus mode and single-bus mode,

wherein the signal switch ensures that data in the memory interface can be accessed in the multi-bus and single-bus modes,

wherein both the signal-to-power switch and signal switch are configured to route signals and power in the multi-bus and single-bus modes,

wherein the signal buffer amplifies the I/O signals in order to offset effects of parasitic capacitance.

15. The circuit of claim 14 , wherein the switchable pins are configured to switch between a power mode and a signal mode.