Semiconductor memory device that includes a refresh control circuit that maintains a refresh cycle when an MRS code signal is changed due to temperature
A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.
1. A semiconductor memory device, comprising:
a memory circuit including a plurality of memory cells; and
a refresh control circuit configured to determine a number of times to perform a target row refresh (TRR) in response to a first mode register set (MRS) code signal, wherein the first MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle for at least two of the memory cells for a period of time when the first MRS code signal is changed due to the temperature change.
2. The device of claim 1 , wherein the number of times to perform the TRR is set to be smaller when a normal refresh cycle is lengthened in response to the first MRS code signal.
3. The device of claim 1 , wherein the number of times to perform the TRR is set to be greater when a normal refresh cycle is shortened in response to the first MRS code signal.
4. The device of claim 1 , wherein the determined number of the TRR is completed in response to the first MRS code signal before performing the TRR in response to a second MRS code signal input after the first MRS code signal.
5. The device of claim 4 , wherein, after the determined number of the TRR is completed in response to the first MRS code signal, the TRR is performed in response to the second MRS code signal.
6. A semiconductor memory device, comprising:
a memory circuit including a plurality of memory cells; and
a refresh control circuit configured to change a refresh cycle of the memory circuit according to a temperature change that occurs while a normal refresh is being performed, wherein a refresh mode is changed responsive to the temperature change after a predetermined delay time measured from an end of the normal refresh,
wherein a mode register set (MRS) code signal is used to indicate the temperature change.
7. The device of claim 6 , wherein the MRS code signal determines a number of times to perform a target row refresh (TRR).
8. The device of claim 7 , wherein the number of times to perform the TRR is determined and the normal refresh are performed in a refresh mode that was set before the temperature change is detected.
9. The device of claim 7 , wherein the determined number of the TRR is performed after the predetermined delay time.