IP Library Granted Patent US 10,103,028
Granted Patent B2
US 10,103,028 · App. 15/417,638 · Granted Oct 16, 2018

Contact integration and selective silicide formation methods

Inventor: Matthias Bauer (Sunnyvale, CA)
Assignee: APPLIED MATERIALS, INC.
H01L21/28518H01L21/02068H01L21/823814H01L21/823871
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Quick Facts
Patent No.
US 10,103,028
App. No.
15/417,638
Granted
Oct 16, 2018
Kind
B2
Abstract

Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550° C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes.

Claims (44)

1. A silicide formation method, comprising:

performing a contact trench etching process to expose source/drain (S/D) regions;

performing a cleaning process on the exposed S/D regions;

performing an epitaxial germanium deposition on the S/D regions, wherein the epitaxially deposited germanium is doped with gallium; and

performing a silicide formation process on the S/D regions by exposing the epitaxially deposited germanium to a titanium containing precursor and a silicon containing precursor at a temperature less than about 550° C.

2. The method of claim 1 , wherein the titanium containing precursor is selected from the group consisting of TiCl 4 , TiBr 4 , and TiI 4 .

3. The method of claim 2 , wherein the titanium containing precursor is TiCl 4 .

4. The method of claim 1 , wherein the silicon containing precursor is selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 , and Si 4 H 10 .

5. The method of claim 4 , wherein the silicon containing precursor is SiH 4 .

6. The method of claim 1 , wherein the titanium containing precursor and the silicon containing precursor are co-flowed during the silicide formation process.

7. The method of claim 1 , wherein the titanium containing precursor and the silicon containing precursor are pulsed in an alternating manner during the silicide formation process.

8. The method of claim 1 , further comprising:

exposing the S/D regions to a germanium hydride material during the silicide formation process.

9. The method of claim 8 , wherein the germanium hydride material is GeH 3 .

10. The method of claim 1 , wherein the silicide formation process is performed by thermal chemical vapor deposition at less than about 500° C.

11. The method of claim 1 , further comprising:

exposing the S/D regions to a chlorine containing precursor during the silicide formation process.

12. The method of claim 11 , wherein the chlorine containing precursor is selected from the group consisting of SiCl 4 , SiCI 3 H, SiCl 2 H 2 , SiCl 2 , SiCIH 4 , HCI, Cl 2 , GeCI 4 , GeCl 2 , and combinations and mixtures thereof.

13. The method of claim 1 , wherein the silicide formation process forms a c54 phase titanium silicide material.

14. The method of claim 13 , wherein the titanium silicide material has a resistivity of between about 13 μΩ/cm 2 and about 16 μΩ/cm 2 .

15. A silicide formation method, comprising:

performing a contact trench etching process to expose source/drain (S/D) regions, wherein the exposed S/D regions comprise Group IV materials;

performing an oxide removal process on the exposed S/D regions;

performing an epitaxial germanium deposition on the S/D regions; and

performing a thermal chemical vapor deposition silicide formation process on the S/D regions by exposing the epitaxially deposited germanium to a titanium containing precursor and a silicon containing precursor at a temperature less than about 500° C. to form a silicide material alloy comprising titanium, silicon, and germanium, wherein the germanium is present in the alloy in a concentration of less than 10%.

16. The method of claim 15 , wherein S/D regions are configured as nMOS type devices.

17. The method of claim 15 , wherein the S/D regions are configured as pMOS type devices.

18. A silicide formation method, comprising:

performing a contact trench etching process to expose pMOS type and nMOS type source/drain (S/D) regions;

performing a first cleaning process on the exposed S/D regions;

masking pMOS type S/D regions;

performing an epitaxial germanium deposition on the pMOS type S/D regions;

removing the mask from the pMOS type S/D regions;

masking nMOS type S/D regions;

performing an epitaxial germanium deposition on the nMOS type S/D regions;

removing the mask from the nMOS type S/D regions;

performing a second cleaning process on the S/D regions; and

performing a silicide formation process on the S/D regions by exposing the epitaxially deposited germanium to a titanium containing precursor and a silicon containing precursor at a temperature less than about 550° C.

19. The method of claim 18 , wherein the silicide formation process forms a silicide material alloy comprising titanium, silicon, and germanium, and wherein the germanium is present in the alloy in a concentration of less than 10%.

20. A silicide formation method, comprising:

performing a contact trench etching process to expose source/drain (S/D) regions;

performing a cleaning process on the exposed S/D regions;

performing an epitaxial germanium deposition on the S/D regions; and

performing a silicide formation process on the S/D regions by exposing the epitaxially deposited germanium to a titanium containing precursor, a chlorine containing precursor, and a silicon containing precursor at a temperature less than about 550° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2017
From: BAUER, MATTHIAS
To: APPLIED MATERIALS, INC.
Reel/Frame 043800/0546 →
Continuity (2)
Provisional Application 62395277 · Sep 15, 2016
Related Publication 20180076041A1 · Mar 15, 2018
Cited By (1)
US 12,727,405