High-efficiency digital signal processing of streaming media

1. A computing device having one or more processors and a memory to store program code which, when executed by the one or more processors, causes the one or more processors to:

reorder a sequence of instructions that is to be iteratively executed within an execution thread to produce a reordered sequence of instructions in which constituent instructions that require longer execution time than other constituent instructions are grouped together; and

insert, within the reordered sequence of instructions, one or more additional instructions to enable parallel execution of two or more instances of the sequence of instructions such that the constituent instructions that require longer execution time will be executed concurrently with the other constituent instructions such that time required for multiple executions of the sequence of instructions is reduced.

2. The computing device of claim 1 wherein the one or more processors are further caused to revise the sequence of instructions, before reordering to produce the reordered sequence of instructions, to eliminate one or more time-consuming memory access operations.

3. The computing device of claim 2 wherein revising the sequence of instructions to eliminate the one or more time-consuming memory access operations comprises replacing a subroutine invocation instruction with an inline instance of instructions that implement the function of the subroutine.

4. The computing device of claim 1 wherein reordering the sequence of instructions comprises relocating the constituent instructions that require longer execution time toward the beginning or end of the reordered sequence of instructions.

5. A computing device having one or more processors and a memory to store program code which, when executed by the one or more processors, causes the one or more processors to:

identify a normalized processor profile having a set of feature common to all processors within a specified set of commercially available processors;

generate, for each of a plurality of algorithms capable of executing a predetermined task, a respective score indicating an estimated cost of the algorithm if executed by the normalized processor;

identify a first algorithm of the plurality of algorithms based at least in part on the respective score for each of the plurality of algorithms; and

incorporate, within a program code product intended to be executed within a variety of host devices each having a different set of one or more of the commercially available processors, program code instructions corresponding to the first algorithm such that aggregate cost of executing the predetermined task within each of the variety of host devices is reduced.

6. The computing device of claim 5 wherein generating a respective score indicating an estimated cost of each algorithm if executed by the normalized processor comprises disassembling the algorithm into instructions executable by the normalized processor.

7. The computing device of claim 6 wherein generating the respective score further comprises extracting metrics from the disassembly into instructions executable by the normalized processor, including determining at least one of a branch count, a parameter count, a variable count or an instruction count.

8. The computing device of claim 7 wherein generating the respective score further comprises generating a plurality of score components based on evaluation of at least one of the branch count, parameter count, variable count or instruction count in view of at least one of a register count, instruction expense or branch concurrency of the normalized processor.

9. The computing device of claim 8 wherein generating the respective score further comprises weighting evaluations of the branch count, parameter count, and instruction count non-uniformly.

10. The computing device of claim 9 further comprising a display and user-input device, and wherein the one or more processors are further caused to prompt a user via the display to enter, via the user-input device, weighting values to be applied in evaluations of the branch count, parameter count and instruction count.

11. The computing device of claim 5 wherein identifying the normalized processor profile having the set of features common to all processors within the specified set of commercially available processors comprises identifying a normalized processor profile having one or more of (i) an executable instruction set consisting of instructions common to instruction sets of all processors within the specified set of commercially available processors, (ii) a quantity of registers that does not exceed a quantity of registers within any processor within the specified set of commercially available processors, or (iii) a branch concurrency capability that does not exceed a branch concurrency capability of any processor within the specified set of commercially available processors.