Digital interconnects with protocol-agnostic repeaters
A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
1. A signal conditioner, comprising:
a data receiver to receive a data stream from a data-stream channel;
a conditioning circuit to modify the data stream according to a variable operating parameter, wherein the conditioning circuit comprises a re-driver to restore a degraded analog signal and a re-timer having a digital data recovery circuit to recover the degraded analog signal, locally generate a transmit clock, and retransmit the signal with the locally generated transmit clock;
a data transmitter to transmit the data-stream after the modifying;
a clock receiver to receive a clock signal from a clock channel, wherein the clock channel is separate from the data-stream channel and the clock signal has a lower data rate than the data stream;
a decoder to extract the operating parameter embedded in the clock signal by modulation and control logic to reconfigure the conditioning circuit in response to a change in the operating parameter extracted by the decoder.
2. The signal conditioner of claim 1 , wherein the conditioning circuit comprises an automatic gain control or a configurable equalizer.
3. The signal conditioner of claim 1 , wherein the data-stream comprises commands from a controller to operate a remote peripheral device.
4. The signal conditioner of claim 3 , wherein the remote peripheral device comprises hardware for input and output of data to and from the controller.
5. The signal conditioner of claim 1 , wherein the modified data-stream has at least one of: increased amplitude or corrected timing, relative to the data-stream.
6. A signal conditioner, comprising:
a data receiver to receive a data stream from a data-stream channel, wherein the data-stream comprises commands from a controller to operate a remote peripheral device;
a conditioning circuit to modify the data stream according to a variable operating parameter, wherein the conditioning circuit comprises a re-driver to restore a degraded analog signal and a re-timer having a digital data recovery circuit to recover the degraded analog signal, locally generate a transmit clock, and retransmit the signal with the locally generated transmit clock;
a data transmitter to transmit the data-stream after the modifying;
a clock receiver to receive a clock signal from a clock channel, wherein the clock channel is separate from the data-stream channel and the clock signal has a lower data rate than the data stream, a decoder to extract the operating parameter embedded in the clock signal by modulation;
and control logic to reconfigure the conditioning circuit in response to a change in the operating parameter extracted by the decoder.
7. The signal conditioner of claim 6 , wherein the conditioning circuit comprises an automatic gain control or a configurable equalizer.
8. The signal conditioner of claim 6 , wherein the remote peripheral device comprises hardware for input and output of data to and from the controller.
9. The signal conditioner of claim 6 , wherein the data-stream after modifying has at least one of: increased amplitude or corrected timing, relative to the data-stream.