Transistor device with gate control layer undercutting the gate dielectric
Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (L eff ) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (X ud ) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (L eff ) and improves the control that the gate has over the channel.
1. An integrated circuit including at least one transistor device, the integrated circuit comprising:
a body including semiconductor material;
a gate structure above the body, the gate structure including a gate electrode and a gate dielectric between the gate electrode and the body;
a source region and a drain region, the body between the source and drain regions, wherein the source and drain regions include semiconductor material that has doping levels in excess of 1E20 cm −3 ; and
a layer between the source region and the body, the layer also between the drain region and the body, the layer having a thickness of 1 to 6 nanometers, wherein the layer includes semiconductor material and has doping levels below 1E20 cm −3 , and wherein the layer is in contact with the gate dielectric;
wherein at least one of the source region or the drain region is not in contact with the gate dielectric.
2. The integrated circuit of claim 1 wherein the layer has a thickness of 3 nanometers.
3. The integrated circuit of claim 1 wherein neither the source region nor the drain region is in contact with the gate dielectric.
4. The integrated circuit of claim 1 wherein the at least one of the source region or the drain region that is not in contact with the gate dielectric is at most 5 nanometers away from the gate dielectric.
5. The integrated circuit of claim 1 wherein one of the source region or the drain region is in contact with the gate dielectric.
6. The integrated circuit of claim 5 wherein the one of the source region or the drain region that is in contact with the gate dielectric is under the gate dielectric such that there is an underlap distance of 1 nanometer with respect to the gate dielectric.
7. The integrated circuit of claim 1 wherein the body is a fin and the body is between two portions of the gate structure.
8. The integrated circuit of claim 1 wherein the body is a nanowire or nanoribbon and the gate structure wraps around the body.