Integrated driver and controller for haptic engine

1. An integrated circuit (IC) chip for driving a mass of a linear resonant actuator using low-latency closed-loop control, the IC chip comprising:

an output driving port to couple the IC circuit with one or more coils of the LRA;

class-D amplifier circuitry configured to provide, through the output driving port to the one or more coils of the LRA, an analog driving signal, which has a pulse-width modulation configured to control a position of the mass as a function of time;

an input sensing port to couple the IC circuit with one or more position sensors of the LRA; and

class-D controller circuitry programmable to

process at least (i) a digital position-monitoring signal relating to position-monitoring information, which is received through the input sensing port from the one or more position sensors of the LRA and corresponds to the mass position, and (ii) a digital drive-monitoring signal relating to the analog driving signal, to obtain a digital driving signal, and

provide the digital driving signal to the class-D amplifier circuitry,

wherein the class-D amplifier circuit is configured to amplify the digital driving signal to obtain the analog driving signal.

2. The IC chip of claim 1 , wherein

the analog driving signal has a frequency larger than 10 kHz and smaller than 100 kHz, and the pulse-width modulation has a haptic bandwidth, and

the digital driving signal has a frequency that is smaller than the frequency of the analog driving signal.

3. The IC chip of claim 2 , wherein the haptic bandwidth is smaller than 1000 Hz.

4. The IC chip of claim 1 , comprising analog front-end (AFE) circuitry configured to

receive an analog driving-monitoring signal that has been measured at the output driving port,

digitize the analog driving-monitoring signal to obtain the digital driving-monitoring signal, and

provide the digital driving-monitoring signal to the class-D controller circuitry.

5. The IC chip of claim 4 , wherein the AFE circuitry is configured to

provide an analog current signal to the one or more position sensors of the LRA,

receive, through the input sensing port from the one or more position sensors of the LRA, an analog position-monitoring signal,

digitize the analog position-monitoring signal to obtain the digital position-monitoring signal, and

provide the digital position-monitoring signal to the class-D controller circuitry.

6. The IC chip of claim 4 , wherein the AFE circuitry comprises

signal conditioning circuitry configured to perform one or more of filtering, offsetting and pre-amplifying of each of the received analog signals, and

at least one analog-to-digital converter (ADC) configured to perform the digitizing of the conditioned analog signals.

7. The IC chip of claim 6 , wherein the ADC is a multi-channel sigma-delta ADC or a successive approximation register (SAR) ADC with MUX.

8. The IC chip of claim 1 , wherein, as part of processing the at least the digital position-monitoring signal and the digital drive-monitoring signal, the class-D controller circuitry is programmable to

estimate a position of the mass as a function of time, and then

use at least the estimated mass position to obtain the digital driving signal.

9. The IC chip of claim 1 , wherein the class-D controller circuitry is programmable to

obtain a b-EMF signal induced in the one or more coils of the LRA as corresponding to off-cycle values of the digital drive-monitoring signal, and

estimate a velocity of the mass as a function of time based on the b-EMF signal.

10. The IC chip of claim 9 , wherein, as part of processing the at least the digital position-monitoring signal and the digital drive-monitoring signal, the class-D controller circuitry is programmable to

estimate a position of the mass as a function of time, and then

use at least the estimated mass position and the estimated mass velocity to obtain the digital driving signal.

11. The IC chip of claim 1 , comprising

(A) an input driving port to couple the IC circuit with a host controller;

(B) a digital controller comprising

(B.I) a programmable processor that comprises

(B.I.a) the class-D controller circuitry, and

(B.I.b) power controller circuitry that is different from the class-D controller circuitry and is programmable to

(B.I.b.i) process at least the digital drive-monitoring signal and a digital desired-position signal, which is received through the input driving port from the host controller and represents a desired position of the mass, to obtain a digital desired-boost signal, and

(B.I.b.ii) delay the digital desired-position signal,

wherein the class-D controller circuitry is programmable to

(B.I.a.i) process, along with the digital position-monitoring signal and the digital drive-monitoring signal, a delayed instance of the digital desired-position signal to obtain the digital driving signal, and

(B.I.a.ii) provide the digital driving signal to a class-D modulator-stage of the class-D amplifier circuitry,

(B.II) boost converter controller circuitry that is different from the digital controller and is configured to process at least the digital desired-boost signal to obtain a digital boost-control signal; and

(C) boost converter circuitry configured to

(C.i) obtain an analog boost signal based on the digital boost-control signal, and

(C.ii) provide the analog boost signal to a class-D power-stage of the class-D amplifier circuitry.

12. The IC chip of claim 11 , wherein the power controller circuitry is programmable to

process at least the digital desired-position signal to obtain a digital noise gating signal, and

provide the digital noise gating signal to the class-D power-stage.

13. The IC chip of claim 11 , comprising

(D) an output sensing port to couple the IC circuit with the one or more position sensors of the LRA; and

wherein the power controller circuitry is programmable to process at least the digital desired-position signal to obtain a digital sensor-activate signal configured to cause the one or more position sensors of the LRA to transition from an active state to a passive state, or from the passive state to the active state.

14. The IC chip of claim 13 , comprising analog front-end (AFE) circuitry, wherein the AFE circuitry comprises current source circuitry configured to produce, or stop producing, a current signal based on the digital sensor-activate signal, so the AFE circuitry can selectively provide, through the output sensing port the current signal to the one or more position sensors of the LRA.

15. A haptic system-in-package (SiP) comprising:

a printed-circuit board (PCB);

the IC chip of claim 11 ; and

the LRA, wherein each of the IC chip and the LRA is mounted on the PCB.

16. A haptic system comprising:

a printed-circuit board (PCB);

the IC chip of claim 11 ; and

the LRA comprising a frame, wherein the IC chip and the PCB are either encompassed by the frame or disposed externally to the frame.

17. A host device comprising:

the haptic system of claim 16 ; and

the host controller.

18. The host device of claim 17 is one of a smartphone, a tablet computer, a laptop computer, or a wearable device.

19. The IC chip of claim 1 , wherein, to obtain the digital driving signal, the class-D controller circuitry is programmable to process, along with the digital position-monitoring signal and the digital drive-monitoring signal, (i) a digital current monitoring signal relating to an analog current signal, which is provided by the class-D amplifier circuitry through the output driving port to the one or more coils of the LRA, and (ii) a digital temperature-monitoring signal relating to temperature-monitoring information, which is received through the input sensing port from the one or more position sensors of the LRA and corresponds to a temperature of the respective sensor as a function of time.

20. The IC chip of claim 1 , comprising:

a plurality of instances of the output driving port to couple the IC circuit with corresponding coils of the LRA;

a plurality of instances of the class-D amplifier circuitry configured to provide, through respective instances of the output driving port to the corresponding coils of the LRA, respective instances of the analog driving signal, which have respective instances of the pulse-width modulation configured to control the position of the mass as a function of time; and

a plurality of instances of the input sensing port to couple the IC circuit with corresponding position sensors of the LRA,

wherein the class-D controller circuitry is programmable to

process at least (i) the plurality of instances of the digital position-monitoring signal relating to position-monitoring information, which are received through the respective instances of the input sensing port from the corresponding position sensors of the LRA and correspond to the mass position, and (ii) the plurality of instances of the digital drive-monitoring signal relating to respective instances of the analog driving signal, to obtain a plurality of instances of the digital driving signal, and

provide the instances of the digital driving signal to the respective instances of the class-D amplifier circuitry,

wherein the instances of the class-D amplifier circuit are configured to amplify the respective instances of the digital driving signal to obtain the corresponding instances of the analog driving signal.

21. The IC chip of claim 20 , wherein the AFE circuitry is configured to

receive a plurality of instances of the analog driving-monitoring signal that have been tapped from respective instances of the analog driving signal at the corresponding instances of the output driving port, and digitize them to obtain the respective instances of the digital driving-monitoring signal,

receive a plurality of instances of the analog position-monitoring signal through the corresponding instances of the input sensing port from the respective position sensors of the LRA, and digitize them to obtain the respective instances of the digital position-monitoring signal, and

provide the plurality of instances of the digital position-monitoring signal and the plurality of instances of the digital driving-monitoring signal to the class-D controller circuitry.

22. The IC chip of claim 21 , wherein the AFE circuitry comprises

a plurality of instances of the signal conditioning circuitry, each instance corresponding to a respective received analog signal,

a multiplexer configured to multiplex the received analog signals, and

the ADC configured to perform the digitizing of the multiplexed analog signals.

23. The IC chip of claim 20 , wherein the class-D controller circuitry is programmable to

obtain a plurality of instances of the b-EMF signal induced in respective coils of the LRA as corresponding to off-cycle values of the respective instances of the digital drive-monitoring signal, and

estimate the velocity of the mass as a function of time based on the instances of the b-EMF signal.

24. The IC chip of claim 23 , wherein

first and second instances of the class-D amplifier circuitry are configured to provide respective first and second instances of the analog driving signal on a one-at-a-time basis, and

the class-D controller circuitry is programmable to obtain (i) a first instance of the b-EMF signal induced in the first coil when the first instance of the analog driving signal is not provided to the first coil while the second instance of the analog driving signal is provided to the second coil, and (ii) a second instance of the b-EMF signal induced in the second coil when the second instance of the analog driving signal is not provided to the second coil while the first instance of the analog driving signal is provided to the first coil.

25. The IC chip of claim 23 , wherein, as part of processing at least the plurality of instances of the digital position-monitoring signal and the plurality of instances of the digital drive-monitoring signal, the class-D controller circuitry is programmable to

estimate a position of the mass as a function of time, and then

use at least the estimated mass position and the estimated mass velocity to obtain the plurality of instances of the digital driving signal.

26. The chip of claim 1 , wherein the class-D controller circuitry and the power controller circuitry are configured as low power programmable processors, as programmable gate arrays or a combination of a low power programmable processor and a programmable gate array.

27. The chip of claim 1 , wherein the class-D controller circuitry and the power controller circuitry comprise memory encoding instructions that, when executed by the class-D controller circuitry and/or the power controller circuitry, cause the class-D controller circuitry and/or the power controller circuitry to process the received digital signals using one or more of an LRA model, a thermal model and a Kalman filter.