Double data rate synchronous dynamic random access memory (“DDR SDRAM”) data strobe signal calibration
In calibrating the phase skew between an SDRAM data strobe (“DQS”) signal and data (“DQ”) signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests may emulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.
1. A method for controlling memory system calibration, comprising:
adjusting a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests;
performing the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory (“SDRAM”), each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, each memory test comprising:
setting a data strobe signal delay for the memory controller to correspond to one of the plurality of phase skew values;
writing a plurality of data words to the SDRAM over the data signal channel;
reading the plurality of data words from the SDRAM over the data signal channel; and
determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM;
determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and
setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.
2. The method of claim 1 , wherein the plurality of data words simulate mission-mode data traffic.
3. The method of claim 2 , wherein the mission-mode data traffic is based on one or more applications.
4. The method of claim 1 , wherein adjusting a data signal driver circuit comprises:
determining whether a higher memory test error count corresponds to a higher data signal driver circuit impedance or a lower data signal driver circuit impedance;
increasing the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a higher data signal driver circuit impedance; and
decreasing the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a lower data signal driver circuit impedance.
5. The method of claim 1 , wherein determining an optimal phase skew value corresponding to a lowest error count comprises:
determining a plurality of memory test passing ranges; and
selecting the optimal phase skew value from a largest memory test passing range of the plurality of memory test passing ranges.
6. The method of claim 1 , wherein the SDRAM comprises double data rate SDRAM (“DDR SDRAM”).
7. The method of claim 1 , wherein the memory system is included in a portable computing device (“PCD”).
8. The method of claim 7 , wherein the PCD comprises at least one of a mobile telephone, a personal digital assistant, a pager, a smartphone, a navigation device, and a hand-held computer with a wireless connection or link.
9. The method of claim 1 , wherein adjusting the data signal driver circuit, performing the plurality of system-level memory tests, determining an optimal phase skew value, and setting the data strobe signal delay are performed during booting of the PCD.
10. The method of claim 1 , wherein adjusting the data signal driver circuit, performing the plurality of system-level memory tests, determining an optimal phase skew value, and setting the data strobe signal delay are performed during manufacturing of the PCD.
11. A system for memory system calibration, the system comprising:
a memory system comprising a memory controller and a synchronous dynamic random access memory (“SDRAM”); and
one or more processors configured to:
adjust a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests;
perform the plurality of system-level memory tests, each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, the one or more processors configured to, for each memory test:
set a data strobe signal delay for the memory controller to correspond to one of the plurality of the phase skew values;
write a plurality of data words to the SDRAM over the data signal channel;
read the plurality of data words from the SDRAM over the data signal channel; and
determine an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM;
determine, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and
set the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.
12. The system of claim 11 , wherein the plurality of data words simulate mission-mode data traffic.
13. The system of claim 12 , wherein the mission-mode data traffic is based on one or more applications.
14. The system of claim 11 , wherein the one or more processors are configured to adjust a data signal driver circuit by being configured to:
determine whether a higher memory test error count corresponds to a higher data signal driver circuit impedance or a lower data signal driver circuit impedance;
increase the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a higher data signal driver circuit impedance; and
decrease the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a lower data signal driver circuit impedance.
15. The system of claim 11 , wherein the one or more processors are configured to determine an optimal phase skew value corresponding to a lowest error count by being configured to:
determine a plurality of memory test passing ranges; and
select the optimal phase skew value from a largest memory test passing range of the plurality of memory test passing ranges.
16. The system of claim 11 , wherein the SDRAM comprises double data rate SDRAM (“DDR SDRAM”).
17. The system of claim 11 , wherein the memory system is included in a portable computing device (PCD”).
18. The system of claim 17 , wherein the PCD comprises at least one of a mobile telephone, a personal digital assistant, a pager, a smartphone, a navigation device, and a hand-held computer with a wireless connection or link.
19. The system of claim 11 , wherein the one or more processors are configured to adjust the data signal driver circuit, perform the plurality of system-level memory tests, determine an optimal phase skew value, and set the data strobe signal delay during booting of the PCD.
20. The system of claim 11 , wherein the one or more processors are configured to adjust the data signal driver circuit, perform the plurality of system-level memory tests, determine an optimal phase skew value, and set the data strobe signal delay during manufacturing of the PCD.
21. A computer program product for controlling memory system calibration, the computer program product comprising processor-executable logic embodied in at least one non-transitory storage medium, execution of the logic by one or more processors of a system configuring the system to:
adjust a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests;
perform the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory (“SDRAM”), each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, the system being configured to, for each memory test:
set a data strobe signal delay for the memory controller to correspond to one of the plurality of the phase skew values;
write a plurality of data words to the SDRAM over the data signal channel;
read the plurality of data words from the SDRAM over the data signal channel; and
determine an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM;
determine, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and
set the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.
22. The computer program product of claim 21 , wherein the plurality of data words simulate mission-mode data traffic.
23. The computer program product of claim 22 , wherein the mission-mode data traffic is based on one or more applications.
24. The computer program product of claim 21 , wherein execution of the logic configures the system to adjust the data signal driver circuit by configuring the system to:
determine whether a higher memory test error count corresponds to a higher data signal driver circuit impedance or a lower data signal driver circuit impedance;
increase the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a higher data signal driver circuit impedance; and
decrease the data signal driver circuit impedance in response to a determination that a higher memory test error count corresponds to a lower data signal driver circuit impedance.
25. The computer program product of claim 21 , wherein execution of the logic configures the system to determine an optimal phase skew value corresponding to a lowest error count by configuring the system to:
determine a plurality of memory test passing ranges; and
select the optimal phase skew value from a largest memory test passing range of the plurality of memory test passing ranges.
26. The computer program product of claim 21 , wherein the SDRAM comprises double data rate SDRAM (“DDR SDRAM”).
27. The computer program product of claim 21 , wherein the memory system is included in a portable computing device (PCD”).
28. The computer program product of claim 27 , wherein the PCD comprises at least one of a mobile telephone, a personal digital assistant, a pager, a smartphone, a navigation device, and a hand-held computer with a wireless connection or link.
29. The computer program product of claim 21 , wherein execution of the logic configures the system to adjust the data signal driver circuit, perform the plurality of system-level memory tests, determine an optimal phase skew value, and set the data strobe signal delay during booting of the PCD.
30. A system for controlling memory system signal calibration, comprising:
means for adjusting a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests;
means for performing the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory (“SDRAM”), each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, the means for performing the plurality of system-level memory tests comprising, for each memory test:
means for setting a data strobe signal delay for the memory controller to correspond to one of the plurality of the phase skew values;
means for writing a plurality of data words to the SDRAM over the data signal channel;
means for reading the plurality of data words from the SDRAM over the data signal channel; and
means for determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM;
means for determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and
means for setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.