Method and apparatus for dense hyper IO digital retention
System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a bit marker; and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern.
1. A specialized computer architecture computing system comprising:
a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system;
a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system;
the computer processor configured to access through the internal system bus data stored in the random access memory storage;
the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and
the computer processor configured to perform operations on the generated unencoded raw data blocks,
wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage.
2. The specialized computer architecture computing system of claim 1 , wherein the computer processor accesses the bit markers from the random access memory storage and maps the bit markers to the unique unencoded data stored in the random access memory storage, and combines the unique unencoded data with a block of other uncoded data to produce a composite uncoded data block to generate the unencoded raw data blocks for the computer processor to perform operations.
3. The specialized computer architecture computing system of claim 1 , wherein the generated unencoded data blocks comprises at least two instances of a unique unencoded data retrieved from the random access memory storage.
4. The specialized computer architecture computing system of claim 3 , wherein the generated unencoded data blocks comprises the at least two unique encoded data retrieved from a common memory location in the random access memory storage.
5. The specialized computer architecture computing system of claim 1 , wherein the random access memory storage is electronically coupled to an alternative energy source configured to provide energy when a primary energy sources fails to provide energy to the random access memory storage.
6. The specialized computer architecture computing system of claim 5 , wherein the alternative energy source is a battery.
7. The specialized computer architecture computing system of claim 5 , wherein the alternative energy source is a super cap.
8. The specialized computer architecture computing system of claim 5 , wherein the alternative energy source is configured to supply energy to the random access storage to maintain data integrity of the random access memory storage for a period of time.
9. The specialized computer architecture computing system of claim 8 , wherein the period of time is at least several months.
10. The specialized computer architecture computing system of claim 1 , wherein the random access memory storage is configured to store encoded data that corresponds to an amount of uncoded data that would exceed the storage capacity of the random access memory storage.
11. The specialized computer architecture computing system of claim 1 , wherein the computer processor utilizes that the random access memory storage in order to support operation of the computer processor for conventional functions.
12. The specialized computer architecture computing system of claim 1 , further comprising a conventional hard drive in electronic communication with the computer processor.
13. The specialized computer architecture computing system of claim 1 , wherein the generated unencoded raw data blocks represent a compound object.
14. The specialized computer architecture computing system of claim 1 , wherein the generated unencoded raw data blocks represent a multi-dimensional data object.
15. The specialized computer architecture computing system of claim 1 , wherein the bit markers are generated using a seed value and a replication rule.
16. The specialized computer architecture computing system of claim 1 , wherein the bit markers are generated using a plurality of other bit markers and a combination rule.
17. The specialized computer architecture computing system of claim 1 , wherein the bit markers are generated using fractal-based mapping.
18. A specialized computer architecture computing system comprising:
a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system;
a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system;
the computer processor configured to access through the internal system bus data stored in the random access memory storage;
the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and
the computer processor configured to perform operations on the generated unencoded raw data blocks,
wherein the computer processor is configured to process a first computer data file and a second computer data file, the first and second computer data files generated by the computer processor by concatenating together a plurality of unique data stored in the random access storage, wherein the first and second computer data files each comprise at least one common unique data retrieved from the random storage.
19. The specialized computer architecture computing system of claim 18 , wherein the first and second computer data files each comprises the at least one common unique data retrieved from a common memory location in the random access memory storage.
20. The specialized computer architecture computing system of claim 18 , wherein the random access memory storage is electronically coupled to an alternative energy source configured to provide energy when a primary energy sources fails to provide energy to the random access memory storage.
21. The specialized computer architecture computing system of claim 20 , wherein the alternative energy source is a battery.
22. The specialized computer architecture computing system of claim 20 , wherein the alternative energy source is a super cap.
23. The specialized computer architecture computing system of claim 20 , wherein the alternative energy source is configured to supply energy to the random access storage to maintain data integrity of the random access memory storage for a period of time.
24. The specialized computer architecture computing system of claim 23 , wherein the period of time is at least several months.
25. The specialized computer architecture computing system of claim 18 , wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage.
26. The specialized computer architecture computing system of claim 25 , wherein the computer processor accesses the bit markers from the random access memory storage and maps the bit markers to the unique unencoded data stored in the random access memory storage, and combines the unique unencoded data with a block of other uncoded data to produce a composite uncoded data block to generate the unencoded raw data blocks for the computer processor to perform operations.
27. The specialized computer architecture computing system of claim 25 , wherein the bit markers are generated using a seed value and a replication rule.
28. The specialized computer architecture computing system of claim 25 , wherein the bit markers are generated using a plurality of other bit markers and a combination rule.
29. The specialized computer architecture computing system of claim 25 , wherein the bit markers are generated using fractal-based mapping.
30. The specialized computer architecture computing system of claim 18 , wherein the generated unencoded raw data blocks comprises at least two instances of a unique unencoded data retrieved from the random access memory storage.
31. The specialized computer architecture computing system of claim 18 , wherein the generated unencoded raw data blocks comprises the at least two instances of a unique encoded data retrieved from a common memory location in the random access memory storage.
32. The specialized computer architecture computing system of claim 18 , wherein the random access memory storage is configured to store encoded data that corresponds to an amount of uncoded data that would exceed the storage capacity of the random access memory storage.
33. The specialized computer architecture computing system of claim 18 , wherein the computer processor utilizes that the random access memory storage in order to support operation of the computer processor for conventional functions.
34. The specialized computer architecture computing system of claim 18 , further comprising a conventional hard drive in electronic communication with the computer processor.
35. The specialized computer architecture computing system of claim 18 , wherein the generated unencoded raw data blocks represent a compound object.
36. The specialized computer architecture computing system of claim 18 , wherein the generated unencoded raw data blocks represent a multi-dimensional data object.