Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch
In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
1. An integrated circuit, comprising:
a plurality of semiconductor devices; and
a plurality of conductive lines connecting the plurality of semiconductor devices, wherein a pitch of the plurality of conductive lines is approximately twenty-eight nanometers, wherein each of the plurality of conductive lines comprises:
a line of a conductive metal; and
a carbon-containing layer positioned directly between the conductive metal and a dielectric material.
2. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises copper.
3. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises a copper alloy.
4. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises gold.
5. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises nickel.
6. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises cobalt.
7. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises silver.
8. The integrated circuit of claim 1 , wherein the plurality of conductive lines comprises ruthenium.
9. An integrated circuit, comprising:
a front end, comprising:
a semiconductor wafer; and
a plurality of semiconductor devices formed on the semiconductor wafer; and
a back end, comprising:
a dielectric layer;
a plurality of conductive lines formed in the dielectric layer, wherein a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers; and
a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines.
10. The integrated circuit of claim 9 , wherein the plurality of conductive lines has a uniform profile.
11. The integrated circuit of claim 9 , wherein the back end further comprises:
a capping layer positioned directly between the dielectric layer and the front end.
12. The integrated circuit of claim 11 , wherein the capping layer comprises silicon nitride.
13. The integrated circuit of claim 11 , wherein the capping layer comprises silicon carbonitride.
14. The integrated circuit of claim 11 , wherein the capping layer comprises silicon oxycarbonitride.
15. The integrated circuit of claim 11 , wherein the dielectric layer comprises a low-k dielectric.
16. The integrated circuit of claim 11 , wherein the dielectric layer comprises an ultra-low-k dielectric.
17. The integrated circuit of claim 11 , wherein the dielectric layer comprises silicon dioxide.
18. An integrated circuit, comprising:
a front end, comprising:
a semiconductor wafer; and
a plurality of semiconductor devices formed on the semiconductor wafer; and
a back end, comprising:
a dielectric layer;
a plurality of conductive lines formed in the dielectric layer, wherein the plurality of conductive lines has a uniform profile and a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers;
a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines; and
a capping layer positioned directly between the dielectric layer and the front end.
19. The integrated circuit of claim 18 , wherein the plurality of conductive lines comprises a plurality of interconnects for electrically connecting a plurality of semiconductor devices in the back end.