IP Library Granted Patent US 10,127,982
Granted Patent B2
US 10,127,982 · App. 15/730,388 · Granted Nov 13, 2018

Volatile memory, memory module including the same, and method for operating the memory module

Inventor: Choung-KI Song (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
G11C14/0018G11C5/141G11C11/005G11C11/4072G11C11/40615G11C14/0009
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Quick Facts
Patent No.
US 10,127,982
App. No.
15/730,388
Granted
Nov 13, 2018
Kind
B2
Abstract

A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.

Claims (10)

1. A volatile memory, comprising:

a clock enables reception unit suitable for receiving a clock enable signal;

a mode setup unit suitable for setting up a self-refresh prevention mode for preventing the volatile memory from entering a self-refresh mode; and

a self-refresh control unit suitable for generating a self-refresh mode signal in response to the clock enable signal and an internal refresh command, while maintaining the self-refresh mode signal in a disabled state in the self-refresh prevention mode when entering the self-refresh mode is indicated by the clock enable signal and the internal refresh command.

2. The volatile memory of claim 1 , further comprising:

a command reception unit suitable for receiving a command;

an address reception unit suitable for receiving an address; and

a command decoding unit suitable for generating an internal mode register set command and the internal refresh command by decoding the command,

wherein the mode setup unit sets up the self-refresh prevention mode based on the internal mode register set command and the address.

3. The volatile memory of claim 1 , wherein the entering of the self-refresh mode is indicated when the clock enable signal is disabled from a logic high level to a logic low level and the self-refresh mode signal is enabled.

Priority Claims (1)
KR 10-2014-0041192 · Apr 7, 2014 · national
Continuity (3)
Division 15183395 · Jun 15, 2016
Division 14488976 · Sep 17, 2014
Related Publication 20180033485A1 · Feb 1, 2018