Voltage regulator circuits with pass transistors and sink transistors

1. A voltage regulator circuit, the circuit comprising:

a pass transistor comprising a gate, a source, and a drain;

an error amplifier comprising an output port coupled to the gate of the pass transistor, a first input port, and a second input port;

a feedback circuit coupled to the drain of the pass transistor, and coupled to the first input port of the error amplifier to provide a feedback voltage at the first input port of the error amplifier;

a sink transistor comprising a gate, a source, and a drain coupled to the drain of the pass transistor;

a sink gate voltage circuit coupled to the gate of the sink transistor to provide a gate voltage at the gate of the sink transistor; and

a pass gate sensing circuit coupled to the output port of the error amplifier to provide current to the sink gate voltage circuit.

2. The voltage regulator circuit of claim 1 , further comprising:

a reference voltage source to provide a reference voltage at the second input port of the error amplifier.

3. The voltage regulator circuit of claim 1 , further comprising:

an input voltage source to provide an input voltage at the source of the pass transistor.

4. The voltage regulator circuit of claim 1 , further comprising:

an output capacitor coupled to the drain of the pass transistor; and

a load coupled to the drain of the pass transistor.

5. The voltage regulator circuit of claim 1 , further comprising:

a buffer comprising an input port coupled to the output port of the error amplifier, and an output port coupled to the gate of the pass transistor.

6. The voltage regulator circuit of claim 1 , wherein the pass gate sensing circuit comprises:

a first transistor comprising a gate, a source, and a drain connected to the gate of the first transistor;

a bias current sink coupled to the drain of the first transistor; and

a second transistor comprising a gate coupled to the gate of the first transistor, a source coupled to the output port of the error amplifier, and a drain coupled to the sink gate voltage circuit and to the gate of the sink transistor.

7. The voltage regulator circuit of claim 6 , wherein the sink gate voltage circuit comprises:

a resistor coupled to the drain of the second transistor.

8. The voltage regulator circuit of claim 7 , wherein the sink gate voltage circuit further comprises:

a diode-connected transistor coupled in series with the resistor.

9. The voltage regulator circuit of claim 8 , wherein the feedback circuit comprises:

a first resistor comprising a first terminal coupled to the drain of the pass transistor, and a second terminal coupled to the first input port of the error amplifier; and

a second resistor comprising a terminal connected to the second terminal of the first resistor.

10. The voltage regulator circuit of claim 1 , wherein the sink gate voltage circuit comprises:

a resistor coupled to the pass gate sensing circuit.

11. The voltage regulator circuit of claim 10 , wherein the sink gate voltage circuit further comprises:

a diode-connected transistor coupled in series with the resistor.

12. The voltage regulator circuit of claim 1 , wherein the feedback circuit comprises:

a first resistor comprising a first terminal coupled to the drain of the pass transistor, and a second terminal coupled to the first input port of the error amplifier; and

a second resistor comprising a terminal connected to the second terminal of the first resistor.

13. The voltage regulator circuit of claim 1 , wherein

the pass transistor is a p-metal-oxide-semiconductor field-effect-transistor (pMOSFET); and

the sink transistor is an n-metal-oxide-semiconductor field-effect-transistor (nMOSFET).

14. A circuit comprising:

a pass transistor comprising a gate, a source, and a drain;

an error amplifier comprising an output port coupled to the gate of the pass transistor, a first input port, and a second input port;

a sink transistor comprising a gate, a source, and a drain connected to the drain of the pass transistor;

a first transistor comprising a gate, a source, and a drain connected to the gate of the first transistor;

a bias current sink connected to the drain of the first transistor; and

a second transistor comprising a gate connected to the gate of the first transistor, a source connected to the output port of the error amplifier, and a drain connected to the gate of the sink transistor.

15. The circuit of claim 14 , further comprising:

a resistor coupled to the drain of the second transistor.

16. The circuit of claim 15 , further comprising:

a diode-connected transistor connected in series with the resistor.

17. The circuit of claim 16 , further comprising:

an input voltage source to source current to the source of the first transistor.

18. A circuit comprising:

a pass transistor comprising a gate, a source, and a drain, the gate to have a voltage;

an error amplifier coupled to the pass transistor to control the gate voltage of the pass transistor, the error amplifier comprising a first input port and a second input port;

a sink transistor comprising a gate, a source, and a drain connected to the drain of the pass transistor, the gate of the sink transistor to have a voltage;

a pass gate sensing circuit coupled to the error amplifier to source an error current; and

a sink gate voltage circuit coupled to the pass gate sensing circuit, the sink gate voltage circuit to provide the gate voltage of the sink transistor in response to the error current.

19. The circuit of claim 18 , further comprising:

a load coupled to the drain of the pass transistor; and

a feedback circuit coupled to the pass transistor to provide a feedback voltage at the first input port of the error amplifier, the feedback voltage in response to the pass transistor providing an output voltage to the load.

20. The circuit of claim 19 , further comprising:

a reference voltage source to provide a reference voltage at the second input port of the error amplifier; and

an input voltage source to provide an input voltage at the source of the pass transistor.