Systems and methods for implementing a synchronous FIFO with registered outputs
Example systems and related methods may relate to a synchronous first-in-first-out (FIFO) data buffer. The synchronous FIFO data buffer may include a counter. The counter may (i) receive a plurality of signals and (ii) output a count of total entries in the FIFO. The FIFO may further include a status generator that may (i) receive the plurality of signals and the count of total entries, and (ii) outputs a status signal. The FIFO may further include a selection generator that may (i) receive the count of total entries, the write signal, and the read signal, and (ii) output a data enable signal and a multiplexor selection signal. The FIFO may further include a scalable N×M flip-flop memory structure. N may be a number of entries in the memory structure and M may be a number of bits using flip-flops.
1. A synchronous first-in-first-out (FIFO) data buffer, comprising:
a counter, wherein the counter receives a plurality of signals comprising a system clock signal, a reset signal, a write signal, and read signal, wherein the counter outputs a count of total entries in the FIFO;
a status generator, wherein the status generator receives the plurality of signals and the count of total entries, and wherein the status generator outputs a status signal;
a selection generator, wherein the selection generator receives the count of total entries, the write signal, and the read signal, and wherein the selection generator outputs a data enable signal and a multiplexor selection signal; and
a scalable N×M flip-flop memory structure, wherein N is a number of entries in the memory structure, wherein M is a number of bits using flip-flops, and wherein each entry of the N entries in the memory structure comprises:
an M bit wide multiplexor, wherein the multiplexor receives the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the memory structure, and wherein the multiplexor outputs write data; and
a flip-flop bank, wherein the flip-flop bank receives the write data, the data enable signal, and the system clock signal, and wherein the flip-flop bank outputs a data output comprising information stored in the flip-flop bank.
2. The synchronous FIFO data buffer of claim 1 , wherein the previous entry in the memory structure is entry N−1.
3. The synchronous FIFO data buffer of claim 1 , wherein the counter comprises a number of flip-flops equal to log 2 (N).
4. The synchronous FIFO data buffer of claim 1 , wherein the counter operates on a rising edge of the system clock signal.
5. The synchronous FIFO data buffer of claim 1 , wherein the status signal consists of either a full signal or an empty signal.
6. The synchronous FIFO data buffer of claim 1 , wherein the flip-flop bank of the scalable N×M flip-flop memory structure stores a number of bits in a range of 1 to M.
7. The synchronous FIFO data buffer of claim 1 , wherein a width of the M bit wide multiplexor of the scalable N×M flip-flop memory structure is 1 to M bits.
8. The synchronous FIFO data buffer of claim 1 , wherein the flip-flop bank of the scalable N×M flip-flop memory structure further stores the write data on a rising edge of the system clock signal.
9. A method for implementing a synchronous first-in-first-out (FIFO) data buffer, comprising:
receiving, via a counter, a plurality of signals comprising a system clock signal, a reset signal, a write signal, and a read signal;
transmitting, via the counter, a count of total entries in the FIFO;
receiving, via a status generator, the plurality of signals and the count of total entries;
transmitting, via the status generator, a status signal;
receiving, via a selection generator, the count of total entries from the counter, the write signal, and the read signal;
transmitting, via the selection generator, a data enable signal and a multiplexor selection signal;
receiving, via an M bit wide multiplexor within one entry of a scalable N×M flip-flop memory structure, the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the scalable N×M flip-flop memory structure, wherein N is a number of entries in the scalable N×M flip-flop memory structure, and wherein M is a number of bits using flip-flops;
transmitting, via the M bit wide multiplexor, write data;
receiving, via a flip-flop bank within one entry of the scalable N×M flip-flop memory structure, the write data, the data enable signal, and the system clock signal; and
transmitting, via the flip-flop bank, a data output comprising information stored in the flip-flop bank.
10. The method of claim 9 , wherein the previous entry in the scalable N×M flip-flop memory structure is entry N−1.
11. The method of claim 9 , wherein the counter comprises a number of flip-flops equal to log 2 (N).
12. The method of claim 9 , wherein the counter operates on a rising edge of the system clock signal.
13. The method of claim 9 , wherein the status signal consists of either a full signal or an empty signal.
14. The method of claim 9 , wherein the flip-flop bank of the scalable N×M flip-flop memory structure stores a number of bits in a range of 1 to M.
15. A tangible, non-transitory computer-readable medium comprising program instructions encoded therein, wherein the program instructions, when executed by one or more processors, cause a printing device to perform a method for implementing a synchronous FIFO data buffer comprising:
receiving, via a counter, a plurality of signals comprising a system clock signal, a reset signal, a write signal, and a read signal
transmitting, via the counter, a count of total entries in the FIFO;
receiving, via a status generator, the plurality of signals and the count of total entries;
transmitting, via the status generator, a status signal;
receiving, via a selection generator, the count of total entries from the counter, the write signal, and the read signal;
transmitting, via the selection generator, a data enable signal and a multiplexor selection signal;
receiving, via an M bit wide multiplexor within one entry of a scalable N×M flip-flop memory structure, the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the scalable N×M flip-flop memory structure, wherein N is a number of entries in the scalable N×M flip-flop memory structure, and wherein M is a number of bits using flip-flops;
sending, via the M bit wide multiplexor, write data;
receiving, via a flip-flop bank within one entry of the scalable N×M flip-flop memory structure, the write data, the data enable signal, and the system clock signal; and
transmitting, via the flip-flop bank, a data output comprising information stored in the flip-flop bank.
16. The tangible, non-transitory computer-readable medium of claim 15 , wherein the previous entry in the scalable N×M flip-flop memory structure is entry N−1.
17. The tangible, non-transitory computer-readable medium of claim 15 , wherein the counter comprises a number of flip-flops equal to log 2 (N).
18. The tangible, non-transitory computer-readable medium of claim 15 , wherein the counter operates on a rising edge of the system clock signal.
19. The tangible, non-transitory computer-readable medium of claim 15 , wherein the status signal consists of either a full signal or an empty signal.
20. The tangible, non-transitory computer-readable medium of claim 15 , wherein the flip-flop bank of the scalable N×M flip-flop memory structure stores a number of bits in a range of 1 to M.