IP Library Granted Patent US 10,147,607
Granted Patent B1
US 10,147,607 · App. 15/685,871 · Granted Dec 4, 2018

Semiconductor pitch patterning

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Quick Facts
Patent No.
US 10,147,607
App. No.
15/685,871
Granted
Dec 4, 2018
Kind
B1
Abstract

A semiconductor pitch patterning can include a method comprising directionally forming a mask material on a first set of spacers. The first set of spacers can be formed on a substrate. The method can include directionally forming a mask material on a surface of the substrate. The method can include selectively forming a second set of spacers on side surfaces of the first set of spacers and a portion of the surface of the substrate. The top portion of each of the second set of spacers remains unetched subsequent to removing portions of the mask material from the top portions of the first set of spacers.

Claims (19)

1. A method for semiconductor pitch patterning, comprising:

directionally forming a mask material on:

a first set of spacers formed on a substrate; and

a surface of the substrate;

selectively forming a second set of spacers on side surfaces of the first set of spacers and a portion of the surface of the substrate;

removing portions of the mask material from top portions of the first set of spacers;

wherein a top portion of each of the second set remains unetched subsequent to removing portions of the mask material from the top portions of the first set of spacers; and

applying an additional directional deposition of an additional mask material on the second set of spacers and the surface of the substrate.

2. The method of claim 1 , further comprising removing portions of the mask material from the surface of the substrate.

3. The method of claim 2 , further comprising removing the first set of spacers.

4. The method of claim 1 , wherein the first set of spacers are formed on the substrate by:

forming a photo resist material on the substrate;

forming the first set of spacers on side surfaces of the photo resist material.

5. The method of claim 4 , further comprising removing the photo resist material.

6. The method of claim 1 , further comprising directionally depositing the mask material via a gas cluster ion beam method.

7. The method of claim 1 , comprising selectively depositing a third set of spacers on side surfaces of the second set of spacers.

8. The method of claim 7 , comprising removing the additional mask material from a top of the second set of spacers and the surface of the substrate.

9. The method of claim 8 , comprising removing the second set of spacers.

10. The method of claim 9 , wherein a quantity of the third set of spacers is four times a quantity of the first set of spacers.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: SANDHU, GURTEJ S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043391/0667 →