Fin-type field effect transistor structure and manufacturing method thereof
View Patent ↗A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.
1. A fin-type field effect transistor, comprising:
a substrate having fins and insulators disposed between the fins, wherein at least one fin of the fins comprises a stop layer embedded within the at least one fin, and the stop layer is located below top surfaces of the insulators;
at least one gate stack, disposed on the fins and on the insulators; and
strained material portions, disposed on the at least one fin and disposed on two opposite sides of the at least one gate stack.
2. The transistor of claim 1 , wherein a material of the stop layer comprises silicon germanium oxide (SiGeOx), silicon germanium (SiGe), silicon oxide (SiOx), silicon phosphide (SiP), silicon phosphate (SiPOx) or a combination thereof.
3. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have vertical side profiles.
4. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension substantially equivalent to the middle critical dimension.
5. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension smaller than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension.
6. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension.
7. The transistor of claim 1 , wherein the stop layer is located within a first portion of the at least one fin that is covered by the at least one gate stack, and the strained material portions are in direct contact with second portions of the at least one fin that are not covered by the at least one gate stack without the stop layer located there-between.
8. A fin-type field effect transistor, comprising:
a substrate having fins thereon, wherein the fins comprise stop layers embedded within the fins respectively;
insulators, disposed on the substrate and between the fins;
at least one gate stack, disposed across the fins, covering the fins and disposed on the insulators; and
strained material portions, disposed on two opposite sides of the at least one gate stack, wherein the stop layers in the fins are separated by the strained material portions.
9. The transistor of claim 8 , wherein a material of the stop layer comprises silicon germanium oxide (SiGeOx), silicon germanium (SiGe), silicon oxide (SiOx), silicon phosphide (SiP), silicon phosphate (SiPOx) or a combination thereof.
10. The transistor of claim 8 , wherein portions of the strained material portions below top surfaces of the insulators have vertical side profiles.
11. The transistor of claim 8 , wherein portions of the strained material portions below top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension substantially equivalent to the middle critical dimension.
12. The transistor of claim 8 , wherein portions of the strained material portions below top surfaces of the insulators have a bottom critical dimension, a middle critical dimension smaller than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension.
13. The transistor of claim 8 , wherein portions of the strained material portions below top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension.
14. A method for forming a fin-type field effect transistor, comprising:
providing a substrate;
forming a stop layer embedded within a first depth of the substrate;
patterning the substrate to a second depth to form trenches in the substrate and fins between the trenches, wherein the second depth is larger than the first depth;
forming insulators in the trenches of the substrate;
forming a stack structure over the substrate and on the insulators, wherein the stack structure covers portions of the fins;
forming recesses in the fins by using the stop layer in the fins as an etching stop layer to remove portions of the fins that are not covered by the stack structure;
forming strained material portions in the recesses between the insulators and at two opposite sides of the stack structure;
removing the stack structure; and
forming a gate stack over the substrate, between the strained material portions and on the insulators, wherein the strained material portions are located at two opposite sides of the gate stack.
15. The method of claim 14 , wherein forming a stop layer comprises performing ion implantation to form the stop layer embedded within the substrate.
16. The method of claim 14 , wherein forming a stop layer comprises performing atomic layer deposition to form the stop layer and then forming a silicon layer on the stop layer.
17. The method of claim 14 , wherein forming recesses in the fins by using the stop layer as an etching stop layer comprises performing at least one anisotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the stop layer is removed, and the recesses in the fins have vertical side profiles.
18. The method of claim 14 , wherein forming recesses in the fins by using the stop layer as an etching stop layer comprises performing an anisotropic etching process and then an isotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the stop layer is removed.
19. The method of claim 14 , wherein forming recesses in the fins by using the stop layer as an etching stop layer comprises performing a main etching process and then a lateral etching process to remove portions of the fins that are not covered by the stack structure until at least the stop layer is removed.
20. The method of claim 14 , wherein forming recesses in the fins by using the stop layer as an etching stop layer comprises performing an isotropic etching process and then an anisotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the stop layer is removed.