Display device and driving method
An object is to reduce power consumption of a display device and to suppress deterioration of display quality. As a transistor provided for each pixel, a transistor including an oxide semiconductor layer is used. Note that off-state current of the transistor can be decreased when the oxide semiconductor layer is highly purified. Therefore, variation in the value of a data signal due to the off-state current of the transistor can be suppressed. That is, display deterioration (change) which occurs when writing frequency of the data signal to the pixel including the transistor is reduced (when a break period is lengthened) can be suppressed. In addition, flickers in display which generates when the frequency of an alternating-current driving signal supplied to a signal line in the break period is reduced can be suppressed.
1. A display device comprising:
a pixel comprising a first transistor and a display element;
a controller comprising a first circuit, a second circuit, a third circuit, a fourth circuit, a first switch, and a second switch; and
a signal line driver circuit,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium and zinc,
wherein one of a source and a drain of the first transistor is electrically connected to the signal line driver circuit,
wherein the first circuit is configured to generate a data signal,
wherein the second circuit is configured to generate a driving signal having a lower frequency than the data signal,
wherein the third circuit is configured to generate a first clock signal,
wherein the fourth circuit is configured to divide the first clock signal to generate a second clock signal,
wherein the first switch is configured to select the data signal or the driving signal to be output to the signal line driver circuit,
wherein the second switch is configured to select the first clock signal when the first switch selects the data signal, and
wherein the second switch is configured to select the second clock signal when the first switch selects the driving signal.
2. The display device according to claim 1 , wherein an off-state current of the first transistor per unit channel width is smaller than or equal to 1×10 −8 A/μm.
3. The display device according to claim 1 , wherein a first off-state current of the first transistor comprising the oxide semiconductor is smaller than a second off-state current of a second transistor comprising an amorphous silicon.
4. The display device according to claim 1 , wherein the controller is configured to output the data signal or the driving signal to the signal line driver circuit selectively.
5. The display device according to claim 1 , wherein a frequency of the first clock signal is the same as a frequency of the data signal.
6. The display device according to claim 1 , wherein a frequency of the second clock signal is the same as a frequency of the driving signal.
7. The display device according to claim 1 , wherein variation in voltage of the driving signal is within a voltage variation range of the data signal.
8. The display device according to claim 1 , wherein the driving signal is an alternating-current driving signal.
9. The display device according to claim 1 , wherein the display element is a liquid crystal element.
10. A display device comprising:
a pixel comprising a first transistor and a display element;
a controller comprising a first circuit, a second circuit, a third circuit, a fourth circuit, a first switch, and a second switch;
a signal line driver circuit; and
a scan line driver circuit,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium and zinc,
wherein a gate of the first transistor is electrically connected to the scan line driver circuit,
wherein one of a source and a drain of the first transistor is electrically connected to the signal line driver circuit,
wherein the first circuit is configured to generate a data signal,
wherein the second circuit is configured to generate a driving signal having a lower frequency than the data signal,
wherein the third circuit is configured to generate a first clock signal,
wherein the fourth circuit is configured to divide the first clock signal to generate a second clock signal,
wherein the first switch is configured to select the data signal or the driving signal to be output to the signal line driver circuit,
wherein the second switch is configured to select the first clock signal when the first switch selects the data signal, and
wherein the second switch is configured to select the second clock signal when the first switch selects the driving signal.
11. The display device according to claim 10 , wherein an off-state current of the first transistor per unit channel width is smaller than or equal to 1×10 −8 A/μm.
12. The display device according to claim 10 , wherein a first off-state current of the first transistor comprising the oxide semiconductor is smaller than a second off-state current of a second transistor comprising an amorphous silicon.
13. The display device according to claim 10 , wherein the controller is configured to output the data signal or the driving signal to the signal line driver circuit selectively.
14. The display device according to claim 10 , wherein a frequency of the first clock signal is the same as a frequency of the data signal.
15. The display device according to claim 10 , wherein a frequency of the second clock signal is the same as a frequency of the driving signal.
16. The display device according to claim 10 , wherein variation in voltage of the driving signal is within a voltage variation range of the data signal.
17. The display device according to claim 10 , wherein the driving signal is an alternating-current driving signal.
18. The display device according to claim 10 , wherein the display element is a liquid crystal element.