Semiconductor device with memory structure
A semiconductor device includes a substrate and a memory structure disposed above the substrate. An embodied memory structure includes a bottom electrode disposed above the substrate, a barrier layer disposed at the bottom electrode, a resistance switching layer disposed on the bottom electrode and above the barrier layer, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. A bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance.
1. A semiconductor device, comprising:
a substrate; and
a memory structure disposed above the substrate, and the memory structure comprising:
a bottom electrode, disposed above the substrate;
a barrier layer, disposed at the bottom electrode;
a resistance switching layer, disposed on the bottom electrode and above the barrier layer, wherein a bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance, and sidewalls of the resistance switching layer and sidewalls of the bottom electrode are aligned to each other; and
a top electrode, disposed on the resistance switching layer and covering the resistance switching layer.
2. The semiconductor device according to claim 1 , further comprising an insulating layer directly contacting entire sidewalls of the resistance switching layer.
3. The semiconductor device according to claim 2 , wherein the insulating layer is made of a material comprising silicon nitrite, silicon oxide, or silicon oxide nitrite.
4. The semiconductor device according to claim 1 , wherein the uppermost surface of the barrier layer is lower than a bottom surface of the resistance switching layer.
5. The semiconductor device according to claim 1 , wherein the distance is equal to or larger than 10Å.
6. The semiconductor device according to claim 1 , wherein the distance is in a range of 10Å to 950Å.
7. The semiconductor device according to claim 1 , further comprising:
an interlayer dielectric (ILD) layer, disposed above the substrate; and
a conductive contact functioning as the bottom electrode, disposed above the substrate and within the ILD layer,
wherein at least the resistance switching layer and the top electrode are disposed above the conductive contact, and the bottom surface of the resistance switching layer is higher than the uppermost surface of the barrier layer.
8. The semiconductor device according to claim 1 , wherein the barrier layer is at least disposed at the sidewalls of the bottom electrode.
9. The semiconductor device according to claim 8 , wherein the resistance switching layer is directly formed on the bottom electrode, and the barrier layer surrounds a bottom surface and parts of the sidewalls of the bottom electrode.
10. The semiconductor device according to claim 9 , wherein the uppermost surface of the barrier layer and a top surface of the bottom electrode are spaced apart by the distance.
11. The semiconductor device according to claim 8 , further comprising:
an interlayer dielectric (ILD) layer, disposed on the substrate; and
a conductive contact, disposed within the ILD layer and functioning as the bottom electrode,
wherein the barrier layer is disposed at sidewalls of the conductive contact.
12. The semiconductor device according to claim 11 , wherein the resistance switching layer is formed within the ILD layer and directly disposed on the conductive contact, and the uppermost surface of the barrier layer and a top surface of the conductive contact are spaced apart by the distance.
13. The semiconductor device according to claim 11 , wherein the barrier layer is formed within the ILD layer, and the uppermost surface of the barrier layer and a top surface of the conductive contact are below a top surface of the ILD layer.