Method and structure for FinFET devices

1. A method, comprising:

receiving a semiconductor substrate and a fin extending from the semiconductor substrate;

forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer;

patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer, and wherein the patterning of the multiple dielectric layers includes completely removing the second charged dielectric layer from the fin; and

forming a gate structure engaging the first portion of the fin.

2. The method of claim 1 , wherein:

the first sheet density is higher than the second sheet density; and

the patterning of the multiple dielectric layers further includes:

forming an isolation feature covering and in direct contact with the second charged dielectric layer; and

recessing the isolation feature and the first and second charged dielectric layers to expose the first portion of the fin.

3. The method of claim 1 , wherein:

the first sheet density is lower than the second sheet density; and

the patterning of the multiple dielectric layers further includes:

forming an isolation feature covering and in direct contact with the first charged dielectric layer; and

recessing the isolation feature and the first charged dielectric layer to expose the first portion of the fin.

4. The method of claim 1 , wherein:

the first portion of the fin provides a channel for an n-type field effect transistor;

the first-type charges are negative charges; and

the second-type charges are positive charges.

5. The method of claim 4 , wherein the first charged dielectric layer contains aluminum oxide and the second charged dielectric layer contains silicon nitride.

6. The method of claim 4 , wherein:

the first sheet density is within a range of 2×10 11 /cm 2 to 1×10 13 /cm 2 ; and

the second sheet density is within a range of 2×10 11 /cm 2 to 1×10 13 /cm 2 .

7. The method of claim 1 , wherein the forming of the multiple dielectric layers includes performing an atomic layer deposition (ALD) process.

8. The method of claim 1 , wherein:

the first portion of the fin provides a channel for an p-type field effect transistor;

the first-type charges are positive charges; and

the second-type charges are negative charges.

9. The method of claim 8 , wherein the first charged dielectric layer contains silicon nitride and the second charged dielectric layer contains aluminum oxide.

10. A method of forming a semiconductor device, comprising:

receiving a substrate including first and second fins extending from the substrate;

depositing a first dielectric layer containing net first-type charges, the first dielectric layer covering the first and second fins;

etching a portion of the first dielectric layer, thereby exposing the second fin;

depositing a second dielectric layer containing net second-type charges that are opposite to the net first-type charges, the second dielectric layer covering the first dielectric layer and the second fin;

completely removing the second dielectric layer from the first fin, thereby exposing the first dielectric layer;

forming an isolation feature covering the first and second dielectric layers; and

recessing the isolation feature and the first and second dielectric layers, thereby uncovering a first portion of the first fin and a first portion of the second fin.

11. The method of claim 10 , wherein the first dielectric layer has a sheet charge carrier density higher than the second dielectric layer.

12. The method of claim 10 , wherein:

the first portion of the first fin provides a channel for an n-type field effect transistor and the first-type charges are negative charges; and

the first portion of the second fin provides a channel for a p-type field effect transistor and the second-type charges are positive charges.

13. The method of claim 12 , wherein:

the first dielectric layer contains aluminum oxide; and

the second dielectric layer contains silicon nitride.

14. The method of claim 10 , wherein the depositing of the first and second dielectric layers is by atomic layer deposition (ALD).

15. A method of forming a semiconductor device, comprising:

receiving a structure having a substrate and first and second fins extending from the substrate, wherein the first fin is in a first region and the second fin is in a second region;

forming a first dielectric layer conformally covering the first and second regions, wherein the first dielectric layer includes first-type charges;

forming a spacer layer conformally covering the first dielectric layer, wherein the spacer layer is electric neutral, and wherein the spacer layer contains a composition selected from silicon oxynitride, silicon carbide nitride, silicon oxide carbide nitride, and a combination thereof;

removing the first dielectric layer from the second region;

after the removing of the first dielectric layer from the second region, forming a second dielectric layer conformally covering the first and second regions, wherein the second dielectric layer includes second-type charges, wherein the first-type charges are opposite to the second-type charges;

forming an isolation feature covering the first and second regions; and

recessing the isolation feature and the first and second dielectric layers, thereby uncovering an upper portion of the first fin and an upper portion of the second fin; and

forming a first gate structure engaging the upper portion of the first fin and a second gate structure engaging the upper portion of the second fin.

16. The method of claim 15 ,

wherein the removing of the first dielectric layer from the second region also includes removing the spacer layer from the second region.

17. The method of claim 15 , wherein the first dielectric layer has a larger thickness than the second dielectric layer.

18. The method of claim 15 , wherein the isolation feature is a shallow trench isolation (STI) feature.

19. The method of claim 15 , wherein the spacer layer has a thickness ranging from about 0.5 nm to about 2 nm.

20. The method of claim 15 , wherein the first dielectric layer has a sheet charge carrier density higher than the second dielectric layer.