Lattice-mismatched semiconductor substrates with defect reduction

1. A structure, comprising:

a substrate including a first semiconductor material;

a dielectric feature embedded in the substrate; and

a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls.

2. The structure of claim 1 , wherein one of the two lower sidewalls defines a first angle with respect to the top surface of the substrate, the first angle being in a range from 45° to 59°.

3. The structure of claim 2 , wherein the bottommost portion of the dielectric feature is lower than a bottommost portion of the two lower sidewalls.

4. The structure of claim 1 , wherein one of the two lower sidewalls comprises a hexagonal crystallographic surface.

5. The structure of claim 1 , wherein one of the two lower sidewalls comprises a (111) crystallographic plane defined by the first semiconductor material.

6. The structure of claim 1 , wherein the second semiconductor material includes dislocations due to the lattice mismatch, the dislocations arising from one of the two lower sidewalls and terminating at another of the two lower sidewalls.

7. The structure of claim 6 , wherein the dislocations propagate in a crystallographic direction parallel to the top surface of the substrate.

8. The structure of claim 7 , wherein the substrate is (001) silicon and the crystallographic direction is a <110> direction defined by the (001) silicon.

9. The structure of claim 1 , wherein the two lower sidewalls intersect at a vertex, thereby defining an inversed triangular groove between the two lower sidewalls, a top width of the inversed triangular groove being at least times a depth of the inversed triangular groove.

10. The structure of claim 9 , wherein the top width of the inversed triangular groove is at least 50 nm.

11. The structure of claim 1 , wherein the two upper sidewalls are non-perpendicular to the top surface of the substrate.

12. The structure of claim 1 , wherein the second semiconductor material includes a plurality of fins, further comprising:

a shallow trench isolation (STI) feature, the STI feature surrounding each of the plurality of fins.

13. A semiconductor structure, comprising:

a semiconductor substrate, the semiconductor substrate having a recess, the recess extending lengthwise in a first direction, a bottom portion of the recess having a V-shape in a plane perpendicular to the first direction;

a dielectric feature embedded in the semiconductor substrate, the dielectric feature surrounding the recess, a bottommost portion of the dielectric feature being lower than a topmost portion of the V-shape; and

a crystalline semiconductor material epitaxially grown in the recess, the crystalline semiconductor material having lattice mismatch to the semiconductor substrate.

14. The semiconductor structure of claim 13 , further comprising:

a plurality of fins extending from the crystalline semiconductor material; and

an isolation feature surrounding the plurality of fins.

15. The semiconductor structure of claim 14 , wherein the dielectric feature surrounds the isolation feature.

16. The semiconductor structure of claim 13 , wherein the bottommost portion of the dielectric feature is lower than a bottommost portion of the V-shape.