Analog to digital converter

1. An analog-to-digital converter (“ADC”), comprising:

an input terminal configured to receive an analog input voltage signal;

a first stage coupled to the input terminal and configured to convert an analog input voltage signal received at the input terminal to a first digital value and an analog residue signal;

a second stage coupled to the first stage and configured to convert the analog residue signal to a time value representing the analog residue signal, wherein the second stage comprises a voltage-to-time stage including a capacitive device configured to selectively charge based on the analog residue signal, and an open loop amplifier having an input terminal receiving an output of the capacitive device;

a third stage coupled to the second stage and configured to convert the time value to a second digital value; and

a controller coupled to the first and third stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

2. The ADC of claim 1 , wherein the voltage-to-time stage further includes a zero crossing detector receiving an output of the open loop amplifier.

3. The ADC of claim 1 , wherein the third stage is configured to generate a pulse in response to the zero crossing detector to provide a time domain representation of the analog residue signal.

4. The ADC of claim 1 , wherein the open loop amplifier does not include a feedback loop.

5. The ADC of claim 4 , wherein the voltage-to-time stage further includes a switching device configured to selectively couple the analog residue signal to a constant current source.

6. The ADC of claim 1 , wherein the first stage is configured convert the analog input voltage signal to the first digital value in the voltage domain.

7. The ADC of claim 4 , wherein the first stage includes a successive approximation register (“SAR”) ADC.

8. The ADC of claim 1 , wherein the controller is configured to delay an output of the first digital value.

9. An analog-to-digital conversion (“ADC”) method, comprising:

receiving an analog input voltage signal;

converting the analog input voltage signal to a first digital value and an analog residue signal;

sampling the analog residue signal with a capacitive device configured to selectively charge based on the analog residue signal;

amplifying the sampled analog residue signal using an open loop amplifier;

converting the amplified analog residue signal to a time value representing the analog residue signal;

converting the time value to a second digital value; and

combining the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

10. The method of claim 9 , wherein the analog input voltage signal is converted to the first digital value in the voltage domain.

11. The method of claim 9 , further comprising detecting a zero crossing of the analog residue signal.

12. The method of claim 9 , wherein the first digital value comprises most significant bits of the digital output signal.

13. The method of claim 9 , wherein the second digital value comprises least significant bits of the digital output signal.

14. An analog-to-digital converter (“ADC”), comprising:

an input terminal;

a voltage-to-time converter including a capacitive element and an open loop amplifier receiving an output of the capacitive element;

a controller coupled to the input terminal, the controller configured to:

convert an analog input voltage signal received at the input terminal to a first digital value and an analog residue signal;

sample the analog residue signal with the capacitive element;

convert the analog residue signal to a time value representing the analog residue signal, including amplifying the sampled residue signal with the open loop amplifier;

convert the time value to a second digital value; and

combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

15. The ADC of claim 14 , wherein the open loop amplifier is inherently linear.

16. The ADC of claim 14 , wherein the voltage-to-time converter is configured to selectively couple the capacitive element to a constant current source to selectively discharge the capacitive element.