Logic circuits including magnetic tunnel junction devices
A logic circuit may include at least one magnetic tunnel junction device including a first layer configured to receive a particular input signal and a second layer connected to a node, and an inverter connected to the node and configured to generate an output signal by inverting a signal of the node, wherein the inverter includes a transistor on a substrate, and the at least one magnetic tunnel junction device is on an upper portion of the transistor. The at least one magnetic tunnel junction device may include first and second magnetic tunnel junction devices configured to receive first and second input signals, respectively. The logic circuit may include a magnetic tunnel junction device and a reference resistor configured to receive a second input signal, the reference resistor connected to the node, the reference resistor having a reference resistance. The logic circuit may be included in an apparatus.
1. A logic circuit comprising:
a magnetic tunnel junction device including a first layer configured to receive a first input signal and a second layer connected to a node;
a reference resistor configured to receive a second input signal, the reference resistor connected to the node, the reference resistor having a reference resistance, the reference resistance is greater than a parallel resistance of the magnetic tunnel junction device and smaller than an anti-parallel resistance of the magnetic tunnel junction device; and
an inverter connected to the node, the inverter configured to generate an output signal based on inverting a signal of the node.
2. The logic circuit of claim 1 , wherein,
the first layer is a pinned layer,
the second layer is a free layer, and
the logic circuit is a NAND gate logic circuit.
3. The logic circuit of claim 1 , wherein,
the first layer is a free layer,
the second layer is a pinned layer, and
the logic circuit is a NOR gate logic circuit.
4. The logic circuit of claim 1 , wherein,
the inverter includes a transistor on a substrate, and
the magnetic tunnel junction device and the reference resistor are on an upper portion of the transistor.
5. The logic circuit of claim 1 , wherein the reference resistance is substantially common with an intermediate value of parallel resistance and anti-parallel resistance of the magnetic tunnel junction device.
6. The logic circuit of claim 1 , wherein,
the magnetic tunnel junction device or the reference resistor are connected to the node.