Implantation process for semiconductor device

1. A method for manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;

performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;

forming a device on the first surface adjacent to the first shallow implantation region;

performing a thinning process on the second surface of the substrate; and

performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region is formed to adjoin the first shallow implantation region, the second implantation process is performed such that at least a portion of the second deep implantation region is separated from the first deep implantation region, and the second deep implantation region is formed to peripherally surround the first deep implantation region.

2. The method of claim 1 , wherein

performing the first implantation process comprises forming a second shallow implantation region in the substrate adjacent to the first surface, wherein the second shallow implantation region is formed to peripherally surround the first shallow implantation region; and

the second deep implantation region is formed to adjoin the second shallow implantation region.

3. The method of claim 2 , wherein the first shallow implantation region is an N-type pinned photodiode, the first deep implantation region is a deep N-type pinned photodiode, the second shallow implantation region is a shallow P-type well, and the second deep implantation region is a deep P-type well.

4. The method of claim 2 , wherein after forming the device, the method further comprises:

forming a P-type pinned photodiode in the first shallow implantation region adjacent to the first surface; and

forming an N + -type implantation region in the second shallow implantation region adjacent to the first surface.

5. The method of claim 4 , wherein after forming the P-type pinned photodiode and the N + -type implantation region, the method further comprises:

forming an interlayer dielectric layer to cover the device and the substrate;

forming a plurality of contacts in the interlayer dielectric layer to electrically connect to the device and the N + -type implantation region respectively;

forming an interconnect layer to cover the interlayer dielectric layer and to electrically connect to the contacts; and

bonding the interconnect layer to a carrier.

6. The method of claim 2 , wherein a dopant concentration of the second deep implantation region at the second surface of the substrate is substantially equal to 0.

7. The method of claim 1 , wherein a dopant concentration of the first deep implantation region at the second surface of the substrate is substantially equal to 0.

8. The method of claim 1 , further comprising, before performing the thinning process, forming a pinned photodiode in the first shallow implantation region.

9. A method for manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;

performing a first implantation process on the substrate from the first surface to form a first shallow implantation region and a second shallow implantation region in the substrate adjacent to the first surface, wherein the second shallow implantation region is formed to peripherally surround the first shallow implantation region;

forming a device on the first surface adjacent to the first shallow implantation region and the second shallow implantation region;

bonding the device to a carrier, wherein the first surface of the substrate is opposite to the carrier;

thinning the substrate from the second surface; and

performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region and the second deep implantation region are formed to respectively adjoin to the first shallow implantation region and the second shallow implantation region, and the second implantation process is performed such that a conductivity type of the second deep implantation region is different from a conductivity type of the first deep implantation region.

10. The method of claim 9 , wherein the first shallow implantation region is an N-type pinned photodiode, the first deep implantation region is a deep N-type pinned photodiode, the second shallow implantation region is a shallow P-type well, and the second deep implantation region is a deep P-type well.

11. The method of claim 10 , wherein between forming the device and bonding the device to the carrier, the method further comprises:

forming a P-type pinned photodiode in the first shallow implantation region adjacent to the first surface; and

forming an N + -type implantation region in the second shallow implantation region adjacent to the first surface.

12. The method of claim 11 , wherein between forming the P-type pinned photodiode and the N + -type implantation region and bonding the device to the carrier, the method further comprises:

forming an interlayer dielectric layer to cover the device and the substrate;

forming a plurality of contacts in the interlayer dielectric layer to electrically connect to the device and the N + -type implantation region respectively; and

forming an interconnect layer to cover the interlayer dielectric layer and to electrically connect to the contacts.

13. The method of claim 12 , wherein forming the device comprises:

forming a gate dielectric layer on the first surface of the substrate;

forming a gate electrode on the gate dielectric layer to form a gate stacked structure;

forming a dielectric layer on a sidewall of the gate stacked structure and the first surface of the substrate;

forming a spacer on the dielectric layer on the sidewall of the gate stacked structure; and

forming a resist protection oxide layer to cover the spacer, the dielectric layer, and the gate electrode.

14. The method of claim 9 , wherein

a dopant concentration of the first deep implantation region at the second surface of the substrate is substantially equal to 0; and

a dopant concentration of the second deep implantation region at the second surface of the substrate is substantially equal to 0.

15. A method for manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;

performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;

forming a device on the first surface adjacent to the first shallow implantation region;

forming an interlayer dielectric layer to cover the device and the first surface of the substrate;

forming an interconnect layer to cover the interlayer dielectric layer and to electrically connect to the device;

bonding the interconnect layer to a carrier, wherein the first surface of the substrate is opposite to the carrier; and

performing a second implantation process on the substrate from the second surface to form a first deep implantation region in the substrate adjacent to the second surface, wherein performing the second implantation process comprises masking a portion of the second surface of the substrate, and the first deep implantation region is formed to adjoin to the first shallow implantation region, wherein the first shallow implantation region is an N-type pinned photodiode and the first deep implantation region is a deep N-type pinned photodiode.

16. The method of claim 15 , wherein between forming the device and forming the interlayer dielectric layer, the method further comprises:

forming a P-type pinned photodiode in the first shallow implantation region adjacent to the first surface.

17. The method of claim 15 , wherein

performing the first implantation process comprises forming a second shallow implantation region in the substrate adjacent to the first surface, wherein the second shallow implantation region is formed to peripherally surround the first shallow implantation region, and the second shallow implantation region is a shallow P-type well; and

performing the second implantation process comprises forming a second deep implantation region in the substrate adjacent to the second surface, wherein the second deep implantation region is formed to adjoin the second shallow implantation region and to peripherally surround the first deep implantation region, and the second deep implantation region is a deep P-type well.

18. The method of claim 17 , wherein between forming the device and forming the interlayer dielectric layer, the method further comprises:

forming an N + -type implantation region in the second shallow implantation region adjacent to the first surface.

19. The method of claim 17 , wherein a dopant concentration of the second deep implantation region at the second surface of the substrate is substantially equal to 0.

20. The method of claim 15 , wherein a dopant concentration of the first deep implantation region at the second surface of the substrate is substantially equal to 0.