IP Library Granted Patent US 10,171,078
Granted Patent B2
US 10,171,078 · App. 14/882,714 · Granted Jan 1, 2019

Nonvolatile memory devices with on die termination circuits and control methods thereof

Inventors: Chul Bum Kim (Seoul, KR); Sangchul Kang (Hwaseong-si, KR); Jinho Ryu (Seoul, KR); Seokcheon Kwon (Yongin-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H03K19/0005G11C5/063G11C7/1057G11C7/1084
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Quick Facts
Patent No.
US 10,171,078
App. No.
14/882,714
Granted
Jan 1, 2019
Kind
B2
Abstract

Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period.

Claims (40)

1. A method of operating a nonvolatile memory device, comprising:

receiving a write command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;

receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein after the receiving the write command and the address, the CLE and the ALE are disabled;

after the CLE and the ALE are disabled, activating an on-die termination mode of the data input/output terminals in response to an initial falling edge of a data strobe signal and before a rising edge of the data strobe signal, the rising edge of the data strobe signal following the initial falling edge of the data strobe signal;

receiving write data in synchronization with the data strobe signal; and

deactivating the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE;

wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals and activating a differential signaling mode of the data strobe signal.

2. The method of claim 1 , wherein before the receiving the write command or the address, the chip enable signal is enabled.

3. The method of claim 1 , wherein the activating the on-die termination mode of the data input/output terminals includes adjusting impedance of the data input/output terminals.

4. The method of claim 1 , further comprising:

detecting a command attribute of the write command; and

activating an on-die termination mode of the data strobe signal in response to the detected command attribute.

5. A method of operating a nonvolatile memory device, comprising:

receiving a read command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;

receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein, after the receiving the read command and the address, the CLE and the ALE are disabled;

after the CLE and the ALE are disabled, activating an on-die termination mode of the data input/output terminals in response to an initial falling edge of a read enable signal;

generating a data strobe signal in response to the read enable signal, wherein the activating the on-die termination mode of the data input/output terminal is before a rising edge of the data strobe signal, the rising edge of the data strobe signal following the initial falling edge of the read enable signal;

outputting data in synchronization with the data strobe signal; and

deactivating the on-die termination mode of the data input/output terminal in response to a transition of at least one of a chip enable signal, the ALE, and CLE;

wherein the activating the on-die termination mode of the data input/output terminals includes adjusting impedance of the data input/output terminals or control signal terminals, activating a pseudo differential signaling mode of the data input/output terminals and activating a differential signaling mode of the read enable signal.

6. The method of claim 5 , wherein before the receiving the read command or the address, the chip enable signal is enabled.

7. The method of claim 6 , further comprising:

detecting a command attribute of the read command; and

activating an on-die termination mode of the read enable signal or the data strobe signal in response to the detected command attribute.

8. A method of operating a nonvolatile memory system including a nonvolatile memory device and a controller, comprising:

providing, by the controller, a write command via data input/output terminals in synchronization with a write enable signal to the nonvolatile memory device during an enable period of a command latch enable signal (CLE);

providing, by the controller, an address via the data input/output terminals in synchronization with the write enable signal to the nonvolatile memory device during an enable period of an address latch enable signal (ALE);

after the providing the write command and the address, disabling the CLE and the ALE by the controller;

after the CLE and the ALE are disabled, by the nonvolatile memory device, activating an on-die termination mode of the data input/output terminals in response to an initial falling edge of a data strobe signal and before a rising edge of the data strobe signal provided by the controller, the rising edge of the data strobe signal following the initial falling edge of the data strobe signal;

providing, by the controller, write data in synchronization with the data strobe signal to the nonvolatile memory device; and

deactivating, by the nonvolatile memory device, the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE;

wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals and activating a differential signaling mode of the data strobe signal.

9. The method of claim 8 , further comprising:

before the providing the write command and the address, enabling the chip enable signal by the controller.

10. The method of claim 8 , wherein the activating the on-die termination mode of the data input/output terminals includes adjusting impedance of the data input/output terminals by the nonvolatile memory device.

11. The method of claim 8 , further comprising:

detecting a command attribute of the write command by the nonvolatile memory device; and

activating an on-die termination mode of the data strobe signal in response to the detected command attribute.

12. The method of claim 1 , wherein the rising edge of the data strobe signal immediately follows the initial falling edge of the data strobe signal.

13. The method of claim 5 , wherein the rising edge of the data strobe signal immediately follows the initial falling edge of the read enable signal.

Priority Claims (1)
KR 10-2010-0109409 · Nov 4, 2010 · national
Continuity (3)
Continuation 13286713 · Nov 1, 2011
Provisional Application 61410115 · Nov 4, 2010
Related Publication 20160036438A1 · Feb 4, 2016
Cited By (2)
US 12,537,036 US 12,554,633