Oversampled continuous-time pipeline ADC with voltage-mode summation

1. A stage in a multi-stage analog-to-digital converter, comprising:

a voltage-output digital-to-analog converter (DAC) to generate a reconstructed voltage input signal from a digital input signal provided by an analog-to-digital converter (ADC) digitizing an input signal to the stage;

a resistor in series with an output of the voltage-output DAC; and

a summation node to sum a delayed voltage input signal and the reconstructed voltage input signal; and

a transconductor to sense a voltage signal at the summation node to generate an output signal of the stage.

2. The stage in claim 1 , further comprising:

a delaying element to generate the delayed voltage input signal from an input signal to the stage.

3. The stage in claim 1 , further comprising:

an inverter to invert a digital output of the ADC to form the digital input signal for the DAC.

4. The stage in claim 1 , further comprising:

a first filtering circuit network coupled to the summation node, wherein the first filtering circuit network comprises at least one of a resistor and capacitor.

5. The stage in claim 1 , further comprising:

a second filtering circuit network in a feedback configuration with respect to the transconductor.

6. The stage in claim 1 , further comprising:

a voltage buffer in series with the transconductor.

7. The stage in claim 1 , further comprising:

an operational amplifier in series with the transconductor.

8. The stage in claim 1 , further comprising:

a plurality of time-interleaved digital-to-analog converters (DACs) to generate the reconstructed voltage input signal from digital input signals provided by a plurality of time-interleaved analog-to-digital converters (ADCs) digitizing an input signal to the stage.

9. The stage in claim 1 , further comprising:

a digital-to-analog converter (DAC) to generate the reconstructed voltage input signal from digital input signals provided by a plurality of time-interleaved analog-to-digital converters (ADCs) digitizing an input signal to the stage.

10. The stage in claim 1 , wherein the stage has one or more of the following frequency responses: a first order low-pass response, a high-order high-pass response, and a bandpass response.

11. The stage in claim 1 , wherein the multi-stage analog-to-digital converter is a continuous-time multi-stage analog-to-digital converter.

12. A method for voltage-mode summation in a stage of a multi-stage analog-to-digital converter, the method comprising:

delaying an input signal to the stage to generate a delayed voltage input signal;

generating a reconstructed voltage input signal from the input signal; and

averaging the delayed voltage input signal and the reconstructed voltage input signal to generate an averaged voltage signal.

13. The method of claim 12 , further comprising:

converting the averaged voltage signal into a current output signal.

14. The method of claim 12 , further comprising:

filtering the averaged voltage signal by one or more filtering circuit networks.

15. The method of claim 12 , wherein generating the reconstructed voltage input signal comprises:

digitizing the input signal to generate a digital input signal; and

generating the reconstructed voltage input signal from the digital input signal.

16. The method of claim 15 , wherein generating the reconstructed voltage input signal further comprises:

inverting the digital input signal prior to generating the reconstructed voltage input signal.

17. An apparatus for analog-to-digital conversion through voltage-mode summation, the apparatus comprising:

means for delaying an input signal to generate a delayed voltage input signal;

means for reconstructing the input signal to generate a reconstructed voltage input signal;

means for averaging the delayed voltage input signal and a reconstructed voltage input signal to generate an averaged voltage signal; and

transconductance means for sensing the averaged voltage signal.

18. A stage in a multi-stage analog-to-digital converter, comprising:

a current-output digital-to-analog converter (DAC) to generate a reconstructed voltage input signal from a digital input signal provided by an analog-to-digital converter (ADC) digitizing an input signal to the stage;

a resistor in parallel with an output of the current-output DAC; and

a summation node to sum a delayed voltage input signal and the reconstructed voltage input signal; and

a transconductor to sense a voltage signal at the summation node to generate an output signal of the stage;

wherein the DAC is a current-output DAC, and the stage further comprises a resistor in parallel with an output of the DAC.

19. The stage in claim 18 , further comprising:

a filtering capacitor connected to the summation node.

20. The stage in claim 18 , further comprising:

an operational amplifier in series with the transconductor, wherein the transconductor and the operational amplifier form a part of an active filter.

21. The stage in claim 20 , further comprising:

a further resistor in a feedback path of the transconductor and the operational amplifier.

22. The stage in claim 20 , further comprising:

a further resistor and a capacitor in parallel negative feedback paths of the operational amplifier.

23. The stage in claim 1 , further comprising:

a grounded resistor at an output of the transconductor to convert a current back to a voltage.

24. The stage in claim 2 , wherein the delaying element comprises a delay line and a resistor.

25. The stage in claim 2 , wherein the delaying element comprises a first resistor, a delay line following the first resistor, and a second resistor following the delay line.