Semiconductor systems performing double-write operations and methods of operating the same

1. A semiconductor system comprising:

a controller configured to have a write buffer storing first write data outputted from a host before the first write data is written into a memory circuit,

wherein the controller is configured to write the first write data stored in the write buffer into the memory circuit under a first condition and configured to double-write the first write data stored in the write buffer into the memory circuit under a second condition;

wherein the first condition corresponds to a case that the memory circuit is in a writable state; and

wherein the second condition corresponds to a case that an amount of data stored in the write buffer is greater than or equal to a predetermined level of a total storage capacity of the write buffer.

2. The semiconductor system of claim 1 , wherein an address of the first write data written into the memory circuit under the first condition is identical to an address of the first write data double-written into the memory circuit under the second condition.

3. The semiconductor system of claim 1 , wherein the first write data stored in the write buffer is transmitted to the memory circuit through a first write route or a second write route.

4. The semiconductor system of claim 3 ,

wherein the first write route is used in writing the first write data into the memory circuit under the first condition; and

wherein the second write route is used in double-writing the first write data into the memory circuit under the second condition.

5. The semiconductor system of claim 1 , wherein if second write data different from the first write data is transmitted to the write buffer under the first and second conditions, the controller stores the second write data into the write buffer.

6. The semiconductor system of claim 5 ,

wherein the controller writes the first write data into the memory circuit under the first condition; and

wherein while the first write data is double-written into the memory circuit under the second condition, the controller writes the second write data into the memory circuit.

7. The semiconductor system of claim 1 , further comprising an error correction code (ECC) encoder configured to perform an ECC encoding operation of the first write data to generate encoded data and configured to store the encoded data into the write buffer.

8. The semiconductor system of claim 1 , further comprising a data selection unit configured to transmit data stored in the write buffer or data outputted from the memory circuit to the host.

9. The semiconductor system of claim 8 , wherein the data selection unit includes a multiplexor having a first input terminal receiving read data stored in the write buffer and a second input terminal receiving read data outputted from the memory circuit.

10. The semiconductor system of claim 9 , wherein the multiplexor is configured to output the read data stored in the write buffer if the read data is stored in the write buffer and configured to output the read data stored in the memory circuit if the read data is not stored in the write buffer.

11. The semiconductor system of claim 10 , further comprising an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data outputted from the multiplexor to generate decoded data and configured to transmit the decoded data to the host.

12. The semiconductor system of claim 1 , wherein the write buffer is realized using a register or a memory which is designed to have a first-in first-out (FIFO) scheme.

13. A semiconductor system comprising:

a write buffer configured to store write data outputted from a host before the write data is written into a memory circuit;

a data selection unit configured to output read data stored in the write buffer or read data stored in the memory circuit; and

a controller configured to control an operation of the write buffer and an operation of the data selection unit,

wherein the controller is configured to write first write data stored in the write buffer into the memory circuit under a first condition and configured to double-write the first write data stored in the write buffer into the memory circuit under a second condition, during a write operation, and

wherein the controller is configured to transmit read data stored in the write buffer to the data selection unit if the read data is stored in the write buffer and configured to transmit read data stored in the memory circuit to the data selection unit if the read data is not stored in the write buffer, during a read operation, and

wherein in the first condition the memory circuit is in a writable state, and in the second condition an amount of data stored in the write buffer is greater than or equal to a level less than or equal to a total storage capacity of the write buffer.

14. The semiconductor system of claim 13 , wherein the data selection unit includes a multiplexor having a first input terminal receiving read data stored in the write buffer and a second input terminal receiving read data outputted from the memory circuit.

15. The semiconductor system of claim 13 , further comprising:

an error correction code (ECC) encoder configured to perform an ECC encoding operation of the write data outputted from the host to generate encoded data and configured to output the encoded data as the first write data which is stored into the write buffer, in response to a control signal outputted from the controller; and

an ECC decoder configured to perform an ECC decoding operation of read data outputted from the data selection unit to generate decoded data and configured to transmit the decoded data to the host, in response to a control signal outputted from the controller.

16. The semiconductor system of claim 13 , wherein the write buffer is realized using a register or a memory which is designed to have a first-in first-out (FIFO) scheme.