IP Library Granted Patent US 10,193,060
Granted Patent B2
US 10,193,060 · App. 15/449,538 · Granted Jan 29, 2019

Magnetoresistive random access memory device and method of manufacturing the same

Inventors: Yoon-Sung Han (Seoul, KR); Ki-Seok Suh (Hwaseong-si, KR); Woo-Jin Kim (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L43/08H01L27/228H01L43/02H01L43/10H01L43/12
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,193,060
App. No.
15/449,538
Granted
Jan 29, 2019
Kind
B2
Abstract

An MRAM device may include an insulating interlayer structure, a lower electrode contact structure and a variable resistance structure. The insulating interlayer may be formed on a substrate. The lower electrode contact structure may extend through the insulating interlayer. The lower electrode contact structure may include a first electrode having a pillar shape and a second electrode having a cylindrical shape on the first electrode. An upper surface of the second electrode may have a ring shape. A variable resistance structure may be formed on the second electrode. The variable resistance structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode sequentially stacked.

Claims (16)

1. A magnetoresistive random access memory (MRAM) device, comprising:

an insulating interlayer on a substrate, the insulating interlayer including an opening therethrough;

a first electrode in a lower portion of the opening, the first electrode having a pillar shape;

a second electrode on a sidewall of the opening, the second electrode contacting an edge portion of the first electrode and vertically protruding from an upper surface of the first electrode, and an upper surface of the second electrode having a ring shape;

an insulation pattern on the second electrode, the insulation pattern filling an upper portion of the opening; and

a variable resistance structure on the second electrode and the insulation pattern, the variable resistance structure including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked, wherein

the variable resistance structure includes a plurality of variable resistance structures,

an upper surface of the insulating interlayer between the plurality of variable resistance structures is lower than the upper surface of the second electrode, and is higher than the upper surface of the first electrode, and

an upper surface of the insulating interlayer under the variable resistance structure is higher than the upper surface of the insulating interlayer between the plurality of variable resistance structures.

2. The MRAM device as claimed in claim 1 , wherein the first electrode includes a conductive material different from a conductive material of the second electrode.

3. The MRAM device as claimed in claim 1 , wherein the first electrode includes tungsten, copper or aluminum.

4. The MRAM device as claimed in claim 1 , wherein the second electrode includes tantalum, titanium, tantalum nitride, titanium nitride, and/or tungsten nitride.

5. The MRAM device as claimed in claim 1 , wherein a length of the first electrode from a bottom to a top thereof is greater than a length of a portion of the second electrode protruding from the upper surface of the first electrode.

6. The MRAM device as claimed in claim 1 , wherein the second electrode is formed on an upper sidewall of the opening and the upper surface of the first electrode, and has a cylindrical shape.

7. The MRAM device as claimed in claim 1 , further comprising a barrier pattern covering a sidewall and a bottom of the first electrode.

8. The MRAM device as claimed in claim 1 , wherein the second electrode covers a sidewall and a bottom of the first electrode and protrudes from the upper surface of the first electrode, and the insulation pattern directly contacts the first electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2017
From: HAN, YOON-SUNG; SUH, KI-SEOK; KIM, WOO-JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 041464/0822 →
Priority Claims (1)
KR 10-2016-0098554 · Aug 2, 2016 · national
Continuity (1)
Related Publication 20180040813A1 · Feb 8, 2018
Cited By (1)
US 12,268,098