IP Library Granted Patent US 10,199,375
Granted Patent B2
US 10,199,375 · App. 15/694,740 · Granted Feb 5, 2019

Storage device and capacitor

Inventor: Kazuhiro Nojima (Yokkaichi Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/0688H01L27/115H01L28/60
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Quick Facts
Patent No.
US 10,199,375
App. No.
15/694,740
Granted
Feb 5, 2019
Kind
B2
Abstract

A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.

Claims (52)

1. A capacitor comprising:

a plurality of first electrode layers that are stacked in a first direction;

a first conductor that extends in the first direction through the plurality of first electrode layers; and

a first insulating layer that extends in the first direction along the first conductor and is located between the first conductor and the plurality of first electrode layers,

wherein the capacitor includes first capacitances that are respectively provided between the first conductor and the plurality of first electrode layers,

wherein a wiring is disposed on top of the plurality of first electrode layers in the first direction.

2. The capacitor according to claim 1 , further comprising:

a second conductor that extends in the first direction through the plurality of first electrode layers; and

a second insulating layer that extends in the first direction along the second conductor and is located between the second conductor and the plurality of first electrode layers,

wherein the capacitor includes a second capacitance, connected to the first capacitances, between the second conductor and the plurality of first electrode layers.

3. The capacitor according to claim 2 , further comprising:

a plurality of second electrode layers that are stacked in the first direction;

a third conductor that penetrates the plurality of second electrode layers in the first direction;

a third insulating layer that extends in the first direction along the third conductor and is located between the third conductor and the plurality of second electrode layers;

a fourth conductor that penetrates the plurality of second electrode layers in the first direction; and

a fourth insulating layer that extends in the first direction along the fourth conductor and is located between the fourth conductor and the plurality of second electrode layers,

wherein the capacitor includes:

a third capacitance, connected to the second capacitance, between the third conductor and the plurality of second electrode layers; and

a fourth capacitance, connected to the third capacitance, between the fourth conductor and the plurality of second electrode layers.

4. The capacitor according to claim 1 , wherein the wiring is electrically connected to each of the plurality of first electrode layers.

5. A storage device comprising a memory region and a capacitor region arranged side by side on an underlayer,

wherein the memory region includes:

a plurality of first electrode layers stacked in a first direction on the underlayer;

a first conductor that extends in the first direction through the plurality of first electrode layers and is electrically connected to the underlayer; and

a first insulating layer that extends in the first direction along the first conductor and is located between the first conductor and the plurality of first electrode layers,

wherein the capacitor region includes:

a plurality of second electrode layers that are stacked in the first direction on the underlayer;

a second conductor that extends in the first direction through the plurality of second electrode layers and is electrically insulated from the underlayer;

a second insulating layer that extends in the first direction along the second conductor and is located between the second conductor and the plurality of second electrode layers;

a third conductor that extends in the first direction through the plurality of second electrode layers and is electrically insulated from the underlayer;

a third insulating layer that extends in the first direction along the third conductor and is located between the third conductor and the plurality of second electrode layers;

a first wiring; and

a second wiring, and

wherein the second conductor is connected to the first wiring and the third conductor is connected to the second wiring that is different from the first wiring.

6. The storage device according to claim 5 , wherein one of the plurality of first electrode layers is positioned at substantially the same level as one of the plurality of second electrode layers in the first direction.

7. The storage device according to claim 5 , wherein the capacitor region includes first capacitances that are respectively provided between the first conductor and the plurality of first electrode layers.

8. The storage device according to claim 7 , wherein the capacitor region further includes a second capacitance, connected to the first capacitances, between the second conductor and the plurality of first electrode layers.

9. The storage device according to claim 8 , further comprising:

a third conductor that penetrates the plurality of second electrode layers in the first direction;

a third insulating layer that extends in the first direction along the third conductor and is located between the third conductor and the plurality of second electrode layers;

a fourth conductor that penetrates the plurality of second electrode layers in the first direction; and

a fourth insulating layer that extends in the first direction along the fourth conductor and is located between the fourth conductor and the plurality of second electrode layers,

wherein the capacitor region includes:

a third capacitance, connected to the second capacitance, between the third conductor and the plurality of second electrode layers; and

a fourth capacitance, connected to the third capacitance, between the fourth conductor and the plurality of second electrode layers.

10. The storage device according to claim 5 , further comprising a wiring electrically connected to each of the plurality of first electrode layers.

11. The storage device according to claim 5 , further comprising:

a third electrode layer stacked on one of the plurality of second electrode layers via the second insulating layer;

a third insulating layer;

a fourth electrode layer stacked on the third electrode layer via the third insulating layer;

a first contact plug electrically connected to each of one of the plurality of first electrode layers and the third electrode layer; and

a second contact plug electrically connected to each of one of the plurality of second electrode layers and the fourth electrode layer.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2017
From: NOJIMA, KAZUHIRO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043906/0426 →
Priority Claims (1)
JP 2017-053512 · Mar 17, 2017 · national
Continuity (1)
Related Publication 20180269203A1 · Sep 20, 2018
Cited By (1)
US 12,293,968