Methods and systems for implementing high bandwidth memory command address bus training
A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.
1. A method for performing Command Address (CA) training on high bandwidth memory (HBM), comprising:
initializing CA training by sending a first instruction through a wrapper serial port on a HBM mixed-signal physical interface (PHY) to set a Dynamic Random Access Memory (DRAM) into a training mode;
sending a training pattern to the DRAM;
reading an output pattern from the DRAM by sending a second instruction via the wrapper serial port on the HBM PHY after sending the training pattern from the DRAM, wherein the second instruction reads contents of the DRAM into the HBM PHY;
determining whether a CA bus timing problem exists by evaluating a comparison result from comparison of the output pattern to an expected output pattern;
adjusting a delay line corresponding to the comparison result;
determining whether CA training is complete; and
ending CA training mode upon detection of a signal.
2. The method of claim 1 , wherein determining whether CA training is complete further comprises:
sending at least one more training pattern to the DRAM if it is determined that the delay line should be further adjusted; and
re-adjusting the delay line corresponding to another evaluation of the comparison result.
3. The method of claim 1 , comprising sending an IEEE 1500 standard test instruction to at least initialize CA training or end CA training rather than using a register.
4. The method of claim 1 , comprising asserting a DDR PHY Interface (DFI) signal to at least initialize CA training or end CA training.
5. The method of claim 1 , wherein the expected output pattern is stored by implementing registers.
6. The method of claim 1 , wherein reading the output pattern comprises sending a test instruction to read a circuit content.
7. The method of claim 1 , wherein the output pattern is received by sending an IEEE 1500 standard test instruction.
8. The method of claim 1 , wherein reading the output pattern further comprises capturing Wrapper Serial Output to store a circuit content.
9. The method of claim 1 , wherein ending a CA training process comprises detecting at least one signal.
10. The method of claim 1 , wherein reading the training pattern from the DRAM comprises setting the DRAM into a Register Mode.
11. The method of claim 1 , wherein sending the training pattern comprises detecting at least one DFI Interface signal.
12. The method of claim 1 , wherein sending the training pattern comprises storing the training pattern in a 30-bit MISR/LSFR circuit.