Thin film transistor and fabrication method thereof, array substrate, and display panel

1. A fabrication method of a thin film transistor, comprising:

forming an active layer on a base substrate, the active layer including a channel region;

forming an amorphous carbon layer on a region of the active layer other than the channel region; and

forming a source electrode and a drain electrode on the amorphous carbon layer, the source electrode and the drain electrode being respectively electrically connected with the active layer through the amorphous carbon layer,

wherein, the forming the active layer on the base substrate and the forming the amorphous carbon layer on the region of the active layer other than the channel region, include:

forming a semiconductor film on the base substrate, forming an amorphous carbon film on the semiconductor film, and forming a photoresist on the amorphous carbon film;

exposing and developing the photoresist with a dual-tone mask to form a photoresist completely-removed region, a photoresist partially-reserved region and a photoresist completely-reserved region, the photoresist completely-reserved region corresponding to a region where the amorphous carbon layer is to be formed, the photoresist partially-reserved region corresponding to the channel region of the active laver, and the photoresist completely-removed region corresponding to other regions;

removing the amorphous carbon film and the semiconductor film in the photoresist completely-removed region by using an etching process, to form the active layer;

performing an ashing process, to remove the photoresist in the photoresist partially-reserved region and thin the photoresist in the photoresist completely-reserved region;

performing another etching process, to remove the amorphous carbon film in the photoresist partially-reserved region, to form the amorphous carbon layer; and

removing the photoresist in the photoresist completely-reserved region.

2. The method according to claim 1 , wherein, after the forming the amorphous carbon layer and before the forming the source electrode and the drain electrode, the method further comprises: annealing the active layer.

3. The method according to claim 2 , wherein, a temperature at which the active layer is annealed is 230° C. to 400° C.

4. The method according to claim 2 , wherein, after the annealing the active layer and before the forming the source electrode and the drain electrode, the method further comprises:

forming a gate insulation layer on the channel region of the active layer.

5. The method according to claim 4 , wherein, a portion of the gate insulation layer that is in direct contact with the active layer is consisted of silicon dioxide.

6. The method according to claim 4 , wherein, the gate insulation layer is formed to be higher than the amorphous carbon layer on the base substrate.

7. The method according to claim 4 , wherein, after the forming the gate insulation layer and before the forming the source electrode and the drain electrode, the method further comprises:

sequentially forming a gate electrode and an insulation layer on the base substrate on which the gate insulation layer is formed, the insulation layer including a via hole for electrically connecting the source electrode and the drain electrode with the amorphous carbon layer.

8. The method according to claim 1 , wherein, a material for forming the active layer is an oxide semiconductor.

9. A thin film transistor, comprising:

an active layer located on a base substrate, the active layer including a channel region;

an amorphous carbon layer located on a region of the active layer other than the channel region; and

a source electrode and a drain electrode located on the amorphous carbon layer and respectively electrically connected with the active layer through the amorphous carbon layer,

wherein, the thin film transistor further comprises: a gate insulation layer, located on the channel region of the active layer, a gate electrode located on the gate insulation layer, and an insulation layer located on the gate electrode: the insulation layer is provided therein with a via hole, and the source electrode and the drain electrode are respectively electrically connected with the amorphous carbon layer located on the region of the active layer other than the channel region through the via hole formed in the insulation layer.

10. The thin film transistor according to claim 9 , wherein, a portion of the gate insulation layer that is in direct contact with the active layer is consisted of silicon dioxide.

11. The thin film transistor according to claim 9 , wherein, the gate insulation layer is formed to be higher than the amorphous carbon layer on the base substrate.

12. The thin film transistor according to claim 9 , wherein, the active layer is formed of an oxide semiconductor.

13. An array substrate, comprising the thin film transistor according to claim 9 .

14. A display panel, comprising the array substrate according to claim 13 .

15. A thin film transistor, comprising:

an active layer located on a base substrate, the active layer including a channel region;

an amorphous carbon layer located on a region of the active layer other than the channel region; and

a source electrode and a drain electrode located on the amorphous carbon layer and respectively electrically connected with the active layer through the amorphous carbon layer,

wherein, the thin film transistor further comprises: a gate insulation layer located on the channel region of the active layer, and the gate insulation layer is formed to be higher than the amorphous carbon layer on the base substrate.