Adaptive compilation and execution for hardware acceleration

1. A method of hardware acceleration, comprising:

selecting, using a processor, a kernel;

determining, using the processor, a clock frequency for the selected kernel;

programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the selected kernel; and

implementing, using the processor, the selected kernel as a kernel circuit within a region of programmable circuitry, wherein the kernel circuit is clocked using the clock signal from the clock circuit having the compatible clock frequency.

2. The method of claim 1 , wherein the clock frequency for the selected kernel is different than a clock frequency for a different kernel available for selection by the processor.

3. The method of claim 1 , wherein the determining the clock frequency for the selected kernel comprises:

reading the clock frequency from metadata included in a container file also including a binary of the selected kernel.

4. The method of claim 3 , wherein the metadata specifying the clock frequency is generated during hardware compilation of the selected kernel.

5. The method of claim 3 , further comprising:

comparing the clock frequency read from the metadata with a table of available clock frequencies for the clock circuit; and

selecting an available clock frequency from the table of clock frequencies as the compatible clock frequency based upon the comparing.

6. The method of claim 1 , further comprising:

responsive to determining that the kernel circuit is inactive, programming the clock circuit to generate the clock signal with a clock frequency lower than the compatible clock frequency.

7. The method of claim 1 , wherein the region of programmable circuitry is a dynamically reconfigurable region of programmable circuitry.

8. The method of claim 1 , wherein the clock circuit is implemented as a hardened circuit or is implemented in a different region of programmable circuitry adapted for static operation.

9. The method of claim 1 , further comprising:

isolating the region of programmable circuitry prior to programming the clock circuit and implementing the kernel within the region; and

de-isolating the region of programmable circuitry responsive to programming the clock circuit and implementing the kernel within the region.

10. A system for hardware acceleration, comprising:

a region of programmable circuitry;

a clock circuit configured to provide a clock signal to the region of programmable circuitry; and

a processor configured to select a kernel and determine the clock frequency for the selected kernel;

wherein the processor is configured to implement the selected kernel within the region of programmable circuitry as a kernel circuit and program the clock circuit to generate the clock signal with a clock frequency compatible with the selected kernel for use in clocking the kernel circuit.

11. The system of claim 10 , wherein the clock frequency for the selected kernel is different than a clock frequency for a different kernel available for selection by the processor.

12. The system of claim 10 , wherein the processor determines the clock frequency for the selected kernel by reading the clock frequency from metadata included in a container file also including a binary for the selected kernel.

13. The method of claim 12 , wherein the metadata specifying the clock frequency is generated during hardware compilation of the selected kernel.

14. The system of claim 12 , wherein the processor is configured to perform executable operations further including:

comparing the clock frequency read from the metadata with a table of available clock frequencies for the clock circuit; and

selecting an available clock frequency from the table of clock frequencies as the compatible clock frequency based upon the comparing.

15. The system of claim 10 , wherein the processor is configured to perform executable operations further including:

responsive to determining that the kernel circuit is inactive, programming the clock circuit to generate the clock signal with a clock frequency lower than the compatible clock frequency.

16. The system of claim 10 , wherein the region of programmable circuitry is a dynamically reconfigurable region of programmable circuitry.

17. The system of claim 10 , wherein the clock circuit is implemented as a hardened circuit or is implemented in a different region of programmable circuitry adapted for static operation.

18. The system of claim 10 , wherein the processor is configured to perform executable operations further including:

isolating the region of programmable circuitry prior to programming the clock circuit and implementing the kernel within the region; and

de-isolating the region of programmable circuitry responsive to programming the clock circuit and implementing the kernel within the region.

19. A computer program product comprising a computer readable storage medium having program code stored thereon, the program code executable by a processor to perform operations comprising:

selecting, using the processor, a kernel;

determining, using the processor, a clock frequency for the selected kernel;

programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the selected kernel; and

implementing, using the processor, the selected kernel as a kernel circuit within a region of programmable circuitry, wherein the kernel circuit is clocked using the clock signal from the clock circuit having the compatible clock frequency.

20. The computer program product of claim 19 , wherein the clock frequency for the selected kernel is different than a clock frequency for a different kernel available for selection by the processor.