Bipolar junction transistor and method of manufacturing the same
A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.
1. A bipolar junction transistor comprising:
a well region disposed in a substrate;
a plurality of emitter regions disposed on the well region in the substrate;
a plurality of first base regions disposed on the well region in the substrate, each of the plurality of first base regions having a ring shape that surrounds a corresponding emitter region;
a common collector region disposed on the well region in the substrate and comprising an outer portion having a ring shape that surrounds the plurality of first base regions and an inner portion disposed between the plurality of first base regions and connected with the outer portion;
a second base region disposed on the well region in the substrate to be electrically connected with the plurality of first base regions by the well region and having a ring shape that surrounds the common collector region;
a plurality of emitter contact regions disposed on the plurality of emitter regions;
a collector contact region disposed on the collector region; and
a base contact region disposed on the second base region.
2. The bipolar junction transistor of claim 1 , wherein the plurality of emitter regions are arranged in a matrix form.
3. The bipolar junction transistor of claim 2 , wherein:
four emitter regions are arranged in a 2×2 matrix form;
the inner portion of the common collector region has a cross shape disposed between the plurality of first base regions.
4. The bipolar junction transistor of claim 1 , further comprising a plurality of device isolation regions, each device isolation region being disposed on a corresponding first base region.
5. The bipolar junction transistor of claim 1 , further comprising a second well region configured to surround the second base region.
6. The bipolar junction transistor of claim 5 , further comprising a well contact region disposed on the second well region.
7. The bipolar junction transistor of claim 6 , further comprising a third device isolation region disposed between the base contact region and the well contact region.
8. The bipolar junction transistor of claim 1 , further comprising a plurality of device isolation regions disposed between the plurality of emitter contact regions and the collector contact region.
9. The bipolar junction transistor of claim 1 , further comprising a second device isolation region disposed between the collector contact region and the base contact region.
10. A method of manufacturing a bipolar junction transistor comprising:
forming a well region in a substrate;
forming a plurality of emitter regions on the well region in the substrate;
forming a plurality of first base regions on the well region in the substrate, wherein each of the plurality of first base regions has a ring shape that surrounds a corresponding emitter region;
forming a common collector region on the well region in the substrate, wherein the common collector region comprises an outer portion having a ring shape that surrounds the plurality of first base regions and an inner portion disposed between the plurality of first base regions and connected with the outer portion;
forming a second base region on the well region in the substrate to be electrically connected with the plurality of first base regions by the well region and having a ring shape that surrounds the common collector region;
forming a plurality of emitter contact regions on the plurality of emitter regions;
forming a collector contact region on the collector region; and
forming a base contact region on the second base region.
11. The method of claim 10 ,
wherein the plurality of first base regions and the second base region are formed simultaneously.
12. The method of claim 10 , further comprising forming a second well region in the substrate to surround the second base region,
wherein the plurality of emitter regions, the collector region, and the second well region are formed simultaneously.
13. The method of claim 12 , further comprising forming a well contact region on the second well region.
14. The method of claim 13 , further comprising forming a third device isolation region between the base contact region and the well contact region.
15. The method of claim 10 ,
wherein the plurality of emitter contact regions and the collector contact region are formed simultaneously.
16. The method of claim 10 , further comprising forming a plurality of device isolation regions between the plurality of emitter contact regions and the collector contact region.
17. The method of claim 10 , further comprising forming a second device isolation region between the collector contact region and the base contact region.