IP Library › Granted Patent US 10,217,853
Granted Patent B1
US 10,217,853 · App. 15/717,975 · Granted Feb 26, 2019

Bipolar junction transistor and method for fabricating the same

Inventor: Chen-Wei Pan (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7393H01L21/2253H01L21/26513H01L21/324H01L29/0657H01L29/0808H01L29/1008H01L29/36H01L29/66325H01L21/76224H01L29/0649H01L29/0821
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Quick Facts
Patent No.
US 10,217,853
App. No.
15/717,975
Granted
Feb 26, 2019
Kind
B1
Abstract

A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Claims (11)

1. A bipolar junction transistor (BJT), comprising:

a substrate having an emitter region, a base region, and a collector region;

a shallow trench isolation (STI) between the emitter region and the base region;

a first well region disposed in the base region; and

a second well region disposed in the emitter region, wherein the first well region and the second well region comprise different concentration and same conductive type, the second well region is directly under part of the STI, and bottom surfaces of the first well region and the second region are coplanar.

2. The bipolar junction transistor of claim 1 , further comprising a deep well region under the emitter region, the base region, and the collector region.

3. The bipolar junction transistor of claim 2 , further comprising a third well region in the collector region.

4. The bipolar junction transistor of claim 3 , wherein the first well region and the second well region comprise a first conductive type and the deep well region and the third well region comprise a second conductive type.

5. The bipolar junction transistor of claim 4 , wherein the first conductive type comprises p-type and the second conductive type comprises n-type.

6. The bipolar junction transistor of claim 1 , further comprising fin-shaped structures on the substrate, wherein the first well region and the second well region are disposed in the fin-shaped structures.

7. The bipolar junction transistor of claim 6 , further comprising a gate structure on each of the emitter region, the base region, and the collector region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2017
From: PAN, CHEN-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 043720/0704 →
Priority Claims (1)
TW 106129133 A · Aug 28, 2017 · national
Cited By (1)
US 12,317,580